Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2006-10-17
2006-10-17
Elmore, Reba I. (Department: 2189)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S206000, C711S221000
Reexamination Certificate
active
07124275
ABSTRACT:
A method for determining a physical address from a virtual address, wherein a mapping regulation between the virtual address and the physical address is implemented as hierarchical tree structure with compressed nodes. First, a compression indicator included in the mapping regulation is read, and a portion of the virtual address associated with the considered node level is read. Using the compression indicator and the portion of the virtual address, an entry in the node list of the considered node is determined. The determined entry is read, whereupon the physical address can be determined directly, if the considered node level has been the hierarchically lowest node level. If higher node levels to be processed are present, the previous steps in determining the physical address for compressed nodes of lower hierarchy level are repeated until the hierarchically lowest node level is reached.
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Gammel Berndt
Ledwa Ralph
May Christian
Sedlak Holger
Baker & Botts L.L.P.
Elmore Reba I.
Infineon - Technologies AG
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