Apparatus and method for detection of address decoder open...

Details Apparatus and method for detection of address decoder open... Apparatus and method for detection of address decoder open...

2007-12-14

2010-06-01

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S200000, C365S230060, C365S189140

Reexamination Certificate

active

07729185

ABSTRACT:
The apparatus comprises derived address generation circuitry, responsive to a base address portion of each base address, to generate an associated series of derived addresses. Each derived address is different from other derived addresses in that associated series and has a derived address portion that differs from the corresponding base address portion by a single address bit value. Read/write sequence generator circuitry is then responsive to each base address in turn, to write in said memory device a first data value at the base address and a second data value at each derived address in the associated series of derived addresses and is arranged to read a data value stored at the base address each time the second data value is written to one of the derived addresses, and to detect an address decoder open fault if the read data value is the second data value.

REFERENCES:
patent: 6400621 (2002-06-01), Hidaka et al.

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