Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
1999-07-21
2001-05-15
Phan, Trong (Department: 2818)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C327S202000
Reexamination Certificate
active
06232796
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to the transfer of data in digital systems. More particularly, this invention relates to a high throughput data transfer technique.
BACKGROUND OF THE INVENTION
It is well known to transmit bits of data between integrated circuit components according to a system clock. Typically, one data bit is transmitted on each clock edge, whereby sampling may occur on the rising or falling edge of the clock signal. Continuing improvements in microprocessor design allow for faster clock speeds, which allow for greater data transmission rates. However, there are practical constraints associated with increasing clock speeds. For example, faster clock speeds result in larger power consumption, thermal dissipation problems, and increased electromagnetic interference.
In view of the foregoing, it would be highly desirable to more fully utilize existing clock speeds. That is, it would be highly desirable to transport more information in response to a clock edge. Such a technique would allows improved processing speeds without increasing clock speed.
SUMMARY OF THE INVENTION
A method of detecting two bits of data transmitted with a single clock edge includes the step of assessing the value of a first data bit and a second data bit transmitted with a single clock edge to generate a first output bit indicative of the value of the first data bit. The assessing step may be implemented by integrating the first data bit and the second data bit, or by identifying signal transitions between the first data bit and the second data bit. The second output bit is produced by simply passing the second data bit.
A circuit to detect two bits of data transmitted with a single clock edge includes a first circuit module to assess the value of a first data bit and a second data bit transmitted with a single clock edge. The first circuit module generates a first output bit indicative of the value of the first data bit. A second circuit module passes the value of the second data bit to produce a second output bit.
The technology of the invention more fully utilizes existing clock speeds by transporting two bits of data every clock edge without using multi-level signaling. Thus, more information is transported in response to a clock edge signal. The technique allows improved processing speeds without increasing clock speed. Advantageously, the invention can be implemented using standard components and is otherwise compatible with most circuit architectures.
REFERENCES:
patent: 4972518 (1990-11-01), Matsuo
patent: 5025174 (1991-06-01), Shikata
patent: 5731715 (1998-03-01), Mote, Jr.
patent: 5936449 (1999-08-01), Huang
patent: 5949251 (1999-09-01), Chambers
patent: 6064232 (2000-05-01), Relph
Batra Pradeep
Sidiropoulos Stefanos
Pennie & Edmonds LLP
Phan Trong
Rambus Incorporated
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