Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-02-16
2001-07-17
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S792000, C375S261000, C375S262000, C375S265000
Reexamination Certificate
active
06263472
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data communication system that incorporates signal point-mapping and signal point-detecting.
One type of digital signal transmitter that has been proposed is illustrated in
FIG. 1
, wherein an information source
1
generates a digital signal to be transmitted. This digital signal is encoded by encoder
2
, an example of which is illustrated in
FIG. 2
, whereby three bits of data (x
3
x
2
x
1
) are encoded into four bits of data (y
3
y
2
y
1
y
0
).
In
FIG. 2
, the 3 bits of input data (x
3
, x
2
, and x
1
) correspond, on a bit-by-bit basis, to the three most significant bits (y
3
, y
2
, and y
1
) of the output of encoder
2
. Registers
11
—
13
and exclusive-OR circuits
14
and
15
use input bits x
2
and x
1
to calculate y
0
, which is the least significant bit of the output data (y
3
, y
2
, y
1
, y
0
).
In particular, bit x
1
and data latched in register
11
are combined by exclusive-OR circuit
14
, and the result is latched into register
12
. The data latched in register
12
and bit x
2
are combined by exclusive-OR circuit
15
, and the result is latched in register
13
. The data in register
13
is provided as output bit y
0
and also is fed back to the input of register
11
. In calculating bit y
0
, encoder
2
does not use the most significant bit x
3
of the input signal or the most significant bit y
3
of the output signal. Since these two bits do not participate in the calculation of bit y
0
, they are deemed to constitute a parallel path. In contrast, bits x
2
and y
2
, and bits x
1
and y
1
do not constitute respective parallel paths because encoder
2
uses them to calculate bit y
0
. In this way, the encoder forms a convolution encoder having an encoding factor of ¾ (ratio of input bits to output bits) and a restriction length of 4 (number of bits in the output).
The output of encoder
2
is supplied to mapping circuit
3
(FIG.
1
), which maps this output according to a Trellis Code Modulation method such as PSK or QAM. Mapping circuit
3
generally comprises a ROM, which is pre-programmed with instructions for carrying out the signal point-mapping method, controlled by a CPU. The output of mapping circuit
3
is supplied to modulator
4
, which then modulates a carrier wave according to the mapped signal; and the output of modulator
4
is transmitted over transmission line
5
.
With respect to mapping circuit
3
, a digital modulation method known as “16 QAM” may be used, for example. This is explained by recognizing that each 4-bit output signal (y
3
y
2
y
1
y
0
) can have any one of 16 possible values (0 to 15), so that the value of each such output signal is mapped to its corresponding signal point, as shown in FIG.
3
. For example, if the output signal has a value of 2 (i.e., 0010 in binary notation), then the value of this output is mapped to signal point S
2
. If the output signal has a value of 8 (1000), it is mapped to signal point S
8
.
The sixteen signal points shown in
FIG. 3
can each be resolved into two mutually perpendicular components, I and Q. The I component can be referred to as the cosine component, and the Q component can be viewed as the sine component. Each signal point is randomly assigned to a particular coordinate value in FIG.
3
. For example, signal point S
9
in
FIG. 3
can be represented by the following equation:
S
9
=3 cos &ohgr;
t+
3 sin &ohgr;
t
(1)
If S
ii
and S
iq
are the equalized I component and Q component, respectively, of the signal point Si, equation (1) above can be generalized by the following formula:
Si=S
ii
×cos &ohgr;
t+S
iq
×sin &ohgr;
t
(2)
where &ohgr; is the angular frequency of the carrier wave, and t is time.
The sixteen signal points S
0
-S
15
shown in
FIG. 3
are mapped from the 4 bits of information (y
3
y
2
y
1
y
0
) by the mapping circuit
3
. According to the results of the mapping, the modulator
4
modulates the amplitude and phase of the carrier wave. That is, the product of the carrier wave and the I component is computed, the product of the carrier wave phase-shifted by 90 degrees and the Q component is computed, and both products are summed to produce an output signal. An encoded output signal (y
3
y
2
y
1
y
0
) that is mapped in accordance with the random arrangement of
FIG. 3
will be vulnerable to noise in transmission line
5
. Such noise is largely, though not exclusively, attributable to temperature variations that occur within the transmission line itself.
In order to reduce this vulnerability to transmission line noise, the 16 signal points are divided into
8
subsets or groups by a so-called set division method. The result of this set division method is illustrated in FIG.
4
.
As shown in
FIG. 4
, the 16 signal points are divided into two subsets such that the distances between the signal points in each subset is maximized. Each subset is divided again into two subsets, and the distances between signal points in each of these subsets is also maximized. Each of these subsets is divided again into two subsets, and the distance between signal points here is also maximized. In this way, each subset is divided until, ultimately, the final subset contains two signal points. As a result, as shown in
FIG. 5
, eight subsets
0
-
7
are derived. Each subset includes two of the signal points of FIG.
3
. For example, subset
0
includes signal point S
0
(which has a value of (0000)) and signal point S
8
(which has a value of (1000)). The signal points are paired in such a way that the three least significant bits of each signal point value in a subset are the same. Moreover, in each subset, the most significant bits of each signal point value (which correspond to the parallel path of
FIG. 17
) always are of opposite values. For example, in subset
0
, the most significant bit of signal point S
0
is “0”, and the most significant bit of signal point S
8
is “1”; furthermore, the three least significant bits of signal points S
0
and S
8
are “000”.
With respect to the remaining subsets, subset
1
contains signal points S
1
(0001) and S
9
(1001). Subset
2
contains signal points S
2
(0010) and S
10
(1010). Subset
3
contains signal points S
3
(0011) and S
11
(1011). Subsets
4
-
7
contain similarly related signal points S
4
and S
12
; S
5
and S
13
; S
6
and S
14
; and S
7
and S
15
.
Within each subset of
FIG. 5
, the signal points can be arbitrarily assigned to each available location. For example, in subset
0
, two signal points S
0
and S
8
can be assigned in such a way that the left upper point shown in
FIG. 6A
is allocated to S
8
, while the point shifted from the center slightly downwardly to the right is allocated to S
0
. As shown in
FIG. 6B
, the reverse allocation is also possible.
In this way, data mapped by the mapping circuit
3
as shown in
FIG. 5
is entered into the modulator
4
. The phase and amplitude of the carrier wave are modulated according to its signal points, and the wave is transmitted over the transmission line
5
. That is, the modulator
4
generates the carrier wave represented by equation (2) above according to the signal point Si for transmission over the transmission line
5
.
The carrier wave thus transmitted over the transmission line is received by a receiver constructed as shown in FIG.
7
. In particular, demodulator
31
detects the I and Q components by performing a quadrature-carrier detection on the received carrier wave. These I and Q components are supplied to decoder
32
, which is composed of a Viterbi decoder, for example. Decoder
32
decodes the I and Q components into the 3 bits of data (x
3
x
2
x
1
) that were originally generated at information source
1
of the digital transmitter.
In order for decoder
32
to decode a received signal point, it must determine to which of the
16
possible signal points of
FIG. 5
the received signal point (which is specified by the I and Q components) corresponds. For example, as shown in
FIG. 8
, let it be assumed that P is a
Frommer William S.
Frommer Lawrence & Haug LLP.
Moise Emmanuel L.
Smid Dennis M.
Sony Corporation
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