Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-08-18
2003-07-29
Hua, Ly V. (Department: 2131)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S042000
Reexamination Certificate
active
06601191
ABSTRACT:
TECHNICAL FIELD
The present invention relates to multistate memory devices, and more specifically, to an apparatus and method for detecting and correcting an over-programming condition in a memory cell of such a device.
BACKGROUND OF THE INVENTION
In conventional single-bit per cell memory devices, the memory cell assumes one of two information storage states, either an “on” state or an “off” state. The binary condition of “on” or “off” defines one bit of information. As a result, a memory device capable of storing n-bits of data requires (n) separate memory cells.
Increasing the number of bits which can be stored using single-bit per cell memory devices depends upon increasing the number of memory cells on a one-for-one basis with the number of bits of data to be stored. Methods for increasing the number of memory bits stored in a memory device composed of single-bit capacity cells have relied upon techniques such as manufacturing larger die which contain more memory cells, or using improved photolithography techniques to build smaller memory cells. Reducing the size of a memory cell allows more cells to be placed on a given area of a single chip.
An alternative to single-bit per cell designs is the storage of multiple-bits of data in a single memory cell. One type of memory in which this approach has been followed is an electrically erasable and programmable device known as a flash memory cell. In flash cells, programming is carried out by applying appropriate voltages to the source, drain, and control gate of the device for an appropriate time period. This causes electrons to tunnel or be injected from a channel region to a floating gate. The amount of charge residing on the floating gate determines the voltage required on the control gate in order to cause the device to conduct current between the source and drain regions. This voltage is termed the threshold voltage, V
th
, of the cell. Conduction represents an “on” or erased state of the device and corresponds to a logic value of one. An “off” or programmed state is one in which current is not conducted between the source and drain regions and corresponds to a logic value of zero. By setting the threshold voltage of the cell to an appropriate value, the cell can be made to either conduct or not conduct current for a given set of applied voltages. Thus, by determining whether a cell conducts current at a given set of applied voltages, the state of the cell (programmed or erased) can be found.
A multi-bit or multistate flash memory cell is produced by creating multiple, distinct threshold voltage levels within the.device. Each distinct threshold voltage corresponds to a set of data bits. This allows multiple bits of binary data to be stored within the same memory cell. When reading the state of the memory cell, each bit set has a corresponding decode value of ones and zeros depending upon the conduction of the device at the threshold voltage level detected. The threshold voltage level for which the cell does not conduct current indicates the bit set representing the data programmed into the cell. Proper data storage requires that the multiple threshold voltage levels of a memory cell be separated from each other by a sufficient amount so that a level of a cell can be programmed or erased in an unambiguous manner. The relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells.
In programming a multistate memory cell, the objective is to apply a programming voltage over a proper time period to store enough charge in the floating gate to move the threshold voltage to a desired level. This level represents a state of the cell corresponding to an encoding of the data which is to be programmed into the cell. It is necessary to be able to program multiple bits (and as a result, multiple memory cells) at the same time in order to produce a commercially desirable memory system which can be programmed within a reasonable amount of time. However, a problem arises when a number of bits are to be programmed at the same time. This is because the characteristics of each bit are different (due to minor variations in the structure and operation of the semiconductor devices which comprise the memory cells), so that variations in the programming speed of different cells will typically occur. This results in bits that become programmed faster than others, and the possibility that some bits will be programmed to a different state (the cell will be programmed to a different threshold voltage level) than intended.
As noted, fast programming of multiple memory cells can result in overshooting the desired threshold voltage state of some cells, producing an error in the data being stored. In some flash memory systems, this problem can remain unknown and result in a long (and unproductive) programming cycle. This can occur because the memory system is controlled to carry out the programming operation until the programming data compares with the data applied or a maximum pulse number, voltage, and programming time occur before it aborts and sets an error flag or performs the programming operation at an alternate storage location. In mass storage systems where programming speed is a key performance criteria and lengthy re-programming and erase operations are not desirable, a method for detecting and handling over-programming of bits during programming operations would be more efficient.
In discussing the problem of over-programming of a multistate memory cell, two primary issues need to be addressed: 1) Overshoot in the threshold voltage level of the cell state (programming a cell to a level corresponding to incorrect data) needs to be detected early in the programming operation in order to stop the programming cycle. This eliminates the time wasted in trying to get the memory cells to achieve a verified threshold voltage level; and 2) An over-programmed cell would normally result in a file being marked as bad or obsolete and written elsewhere in the memory array. A procedure that allows recovery (correction) of the bad cells in a multistate device will save the reprogramming effort and boost performance, allowing for more efficient use of the programming time and storage capacity.
The first issue is not a problem when dealing with conventional two-state memory cells. When detecting an erased state compared to a programmed state, the only requirement is to detect that the programming operation progressed far enough that a programmed charge reference level was exceeded, so that the cell would indicate a programmed state when read. For the two-state memory cell, a program verify sequence consists of carrying out a program operation on the memory cell, then reading the programmed data and comparing it with the desired state (original) of the data being written. If this compare step fails, the cell is given another programming pulse and a compare operation is again performed to see how the programmed data compares with the original data. This sequence is repeated for two-state memory systems until all cells compare, at which time a programming operation is considered successful, or until the number of programming attempts reaches a pre-set limit and the programming operation is aborted.
In multistate memory devices, there are intermediate states that are programmed by setting specific threshold voltage levels within small variations. If the conventional approach to programming is used (a read and compare is performed), a cell that is over-programmed beyond the desired threshold voltage level will never compare properly. The failure of the compare operation will cause the memory cell to be repeatedly programmed, in an attempt to get the error bit to agree to the desired data. The bit failing the compare operation will cause a continuation of the program and compare cycles until the maximum number of programming attempts is reached. This wastes precious time and is an inefficient way of using the memory system.
There is another possible scenario wher
Chevallier Christophe J.
Norman Robert D.
Hua Ly V.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
Apparatus and method for detecting over-programming... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for detecting over-programming..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for detecting over-programming... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3056598