Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Patent
1994-04-08
1997-01-21
Saadat, Mahshid
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
257313, 257532, H01L 2358
Patent
active
055962076
ABSTRACT:
A technique for quantifying the effect of plasma/etching during the formation of MOS transistors avoids the problems of prior techniques. A modified MOS capacitor 40 comprising a dielectric 12 separating a conductive plate 18 having a conductive sidewall 24 from a conductive substrate 10 is formed using the same or similar steps as a MOS transistor. Dielectric layer 12, such as oxide, is formed over a portion of conductive substrate 10. Conductive capacitor plate 18 is formed over a portion of the dielectric layer 12 using a plasma etch to remove unwanted material. After forming capacitor plate 18, the area of capacitor plate 18 is modified to encompass a peripheral oxide region 20. The modification consists of placing a conductive sidewall 24 of the same material as capacitor plate 18 or of other conductive materials around the periphery of capacitor plate 18. Electrical characterization is performed on modified MOS capacitor 40 yielding information about damage to the oxide in peripheral region 24 caused by the plasma etch. Modified MOS capacitor 40 can be used to compare plasma chemistries, detect oxide trenching, detect etchant loading and determine the effect of process hardware changes, for example. It can especially account for oxide loss in tight geometry features and in regimes where optical measurement techniques are unreliable.
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Sodini et al., "Enhanced Capacitor for One-Transistor Memory Cell," IEEE Transactions on Electron Devices, Oct. 1976, pp. 1187-1189.
Krishnan Srikanth
McKee Jeffrey A.
Bowers Courtney A.
Kesterson James C.
Laws Gerald E.
McClure C. Alan
Saadat Mahshid
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