Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-09-26
2003-07-08
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06591408
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and method for designing a semiconductor integrated circuit, more particularly to an apparatus and method for designing clock line. The present invention also relates to a recording medium storing a program for designing a semiconductor integrated circuit, more particularly, to a recording medium storing a program for designing clock line.
2. Description of the Related Art
Top-down design and bottom-up design have been known as methods for designing a semiconductor integrated circuit.
The top-down design is to design functional blocks on a semiconductor integrated circuit in accordance with timing design and desired clock skew.
In the top-down design, since design of the functional blocks depends on the requirements of the whole circuit, one functional block requires plural sets of wiring patterns for various semiconductor circuits. In a semiconductor circuit designed by the top-down design, the same functional blocks may have different wiring patterns. Such the differences in the wiring patterns bring differences in performance among the functional blocks. As a result, function or performance of the circuit as a whole may be deteriorated.
By the bottom-up design, each functional block is designed in accordance with its own timing design and desired clock skew, then a semiconductor integrated circuit is designed with using thus designed functional blocks. Unexamined Japanese Patent Application KOKAI Publication No. H10-135342 discloses a technique for designing functional blocks, wherein cells on a functional block are arranged, and wiring other than clock line is designed so as to be formed on wiring layers other than a top layer and clock line is designed so as to be formed on the top wiring layer.
Each functional block on a semiconductor integrated circuit designed by the bottomup design is designed so as to minimize clock skew of each functional block. According to this structure, clock skews of the functional blocks are not equal. For realizing desired performance of a semiconductor integrated circuit, clock skews must be coincided with each other. In this case, the maximum clock skew is the reference for the coincidence. Extension of inter-block clock line or a buffer for clock skew adjustment are required for adjusting clock skews. Such the wiring extension may bring wiring delay and occupies spaces for other wiring. Those are negative factors for the circuit's performance.
Unexamined Japanese Patent Application KOKAI Publication No. H8-30655 discloses a technique based on the bottom-up design, wherein a semiconductor integrated circuit is designed with using functional blocks each having a synchronizing element in which a delay adjuster area is prepared. Ready-made adjuster elements for adjusting various clock skews are installed in the delay adjuster area. According to this technique, appropriate adjuster elements are installed in the delay adjuster area after functional blocks are arranged on a semiconductor integrated circuit in order to adjust clock skews of the semiconductor integrated circuit.
Since the ready-made adjuster elements are used in the above technique, it is difficult to adjust clock skews finely. If fine-adjustment of the clock skews is unavailable, it is difficult to design a semiconductor integrated circuit which shows desired performance.
Unexamined Japanese Patent Application KOKAI Publication No. H8-221473 discloses a technique, wherein functional blocks are temporarily arranged on a semiconductor integrated circuit, and tentative inter-block clock line is determined. Then, inter-block delay time and intra-block delay time are obtained. Finally, positions of the cells in each functional block, intra-block wiring, and inter-block wiring are shifted and fixed.
According to this technique, since cells in a functional block are shifted, desired performance of the functional block may be unavailable. As a result, it takes many steps for designing the circuit, because the functional block designed under this technique often requires re-designing.
This specification includes the techniques disclosed in Unexamined Japanese Patent Application KOKAI Publication Nos. H8-30655, H8-221473 and H10-135342.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an apparatus and method for efficient design of a semiconductor integrated circuit with satisfying predetermined conditions. It is another object of the present invention to provide a recording medium storing a program for efficient design of a semiconductor integrated circuit with satisfying predetermined conditions.
To achieve the above objects, a design apparatus according to a first aspect of the present invention comprises:
a block layout design unit which designs layout of a plurality of functional blocks within a predetermined area in a semiconductor integrated circuit, wherein clock lines on each of the functional blocks have been laid out so that clock skew of each functional block is minimized;
a wiring erasing unit which pre-designed erases clock lines in the functional blocks laid out in the predetermined area; and
an on-circuit wiring layout design unit which determines clock line paths in the functional blocks from which the clock lines are erased, and determines clock lines among the functional blocks, so that clock skew of whole semiconductor integrated circuit satisfies predetermined conditions.
According to this invention, it is able to design a semiconductor integrated circuit which satisfies predetermined conditions with ease.
The on-circuit wiring layout design unit may determine clock lines over the semiconductor integrated circuit with targeting an upper wiring layer.
The on-circuit wiring layout design unit may comprise:
a draft unit which generates a clock tree to draft paths of the clock lines; and
a path adjuster unit which adjusts the drafted paths so that clock skew of whole semiconductor integrated circuit satisfies predetermined conditions.
The design apparatus may further comprise a block design unit which designs the plurality of the functional blocks.
The block design unit may comprise:
a cell layout design unit which lays out a plurality of cells of a functional block;
an in-block wiring layout design unit which determines clock line paths in the functional block so that clock skew of the functional block satisfies predetermined conditions; and
a wiring layout design unit which determines wiring paths other than the clock line paths in accordance with timing design of the functional block.
A design method according to a second aspect of the present invention comprises:
designing layout of a plurality of functional blocks of a semiconductor integrated circuit in a predetermined area, wherein clock line paths are laid out on each of the functional blocks so that clock skew of each functional block satisfies predetermined conditions;
erasing pre-designed clock lines in the functional blocks laid out in the predetermined area; and
determining clock line paths in the functional blocks from which the pre-designed clock lines are erased, and clock lines among the functional blocks so that clock skew of whole semiconductor integrated circuit satisfies predetermined conditions.
The determining clock line paths in the functional blocks and clock line paths among the functional blocks may comprise determining clock line paths over the semiconductor integrated circuit with targeting an upper wiring layer.
The determining clock line paths in the functional blocks and clock line paths among the functional blocks may comprise:
generating a clock tree to draft paths of the clock lines; and
adjusting the drafted paths so that clock skew of whole semiconductor integrated circuit satisfies predetermined conditions.
The design method may further comprise designing the plurality of the functional blocks.
The designing the functional blocks may comprise:
designing layout of a plurality of cells of the functional blocks;
determining paths of clock lines in each of th
Katten Muchin Zavis & Rosenman
NEC Electronics Corporation
Smith Matthew
Tat Binh C.
LandOfFree
Apparatus and method for designing semiconductor circuit,... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for designing semiconductor circuit,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for designing semiconductor circuit,... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3025100