Electrical computers and digital data processing systems: input/ – Interrupt processing – Source or destination identifier
Reexamination Certificate
1999-04-14
2002-10-22
Myers, Paul R. (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
Source or destination identifier
Reexamination Certificate
active
06470408
ABSTRACT:
TECHNICAL FIELD
The invention is directed to an apparatus and a method that distributes interrupts. In particular, the invention is directed to an apparatus and a method that converts interrupt transactions on a system bus into interrupt mechanisms supported by Intel® Architecture (IA-32) processors.
BACKGROUND ART
Multiprocessor computers implement varying levels of symmetry. Master-slave processor computer systems are very. asymmetric, whereas in computers designed with higher levels of symmetry, each of the working processors are capable of performing the same functions. In symmetric computers, the working processors share buses, address the same memory and basic input/output system (BIOS) resources, and receive the same array of interrupts. However, in current computer systems, no mechanism exists to distribute interrupts to an IA-32processor when mixed with an IA-64 architecture.
SUMMARY OF INVENTION
A computer system provides a mechanism to distribute interrupts from a system bus to Intel® Architecture (IA-)32 processors. The system includes a number of applications processors that are coupled together by an advanced programmable interrupt controller (APIC) bus and by an advanced processor bus. As many as four applications processors can be so coupled. A bridge couples the processor bus and the APIC bus to the system bus. The bridge translates interrupt transactions between the applications processors and the system bus.
The system may include any number of applications processors and bridges. A combination of up to four applications processors and a bridge forms a node. The nodes are coupled together on the system bus. Each applications processor has a unique address related to a nodeID of the processor and a further processor ID. In an improvement over current computer architectures, more than sixteen applications processors may be included in the system.
The system uses the above-described architecture to assert, acknowledge and process the interrupts. Interrupts are forced transfers of execution from a currently running program or task to a special program or task called an interrupt handler. Each of the applications processors may be provided with an interrupt handler in software. Each also may be provided with an APIC to process the interrupts. The applications processors can receive interrupts from other applications processors, or from external devices, such as a keyboard, for example. The source of the interrupt determines some features of the interrupt handling.
In an embodiment, the system uses a bridge to convert interrupt transactions on the system bus into APIC messages that are delivered to a target APIC bus. The bridge monitors the system bus and determines when a particular interrupt transaction is directed to an applications processor at the bridge's node. The bridge may acquire the interrupt transaction, convert the interrupt transaction to an APIC message and send the APIC message to the appropriate applications processor over the APIC bus.
For external interrupts, when the applications processor is able to receive the interrupt, the applications processor will return an interrupt acknowledge over the processor bus. The bridge then provides the interrupt acknowledge to the system bus and the device that generated the external interrupt returns the interrupt vector. With the interrupt vector, the applications processor is able to acquire the interrupt and to execute it using the interrupt handler.
Normal interrupts are delivered to the applications processor as APIC messages over the APIC bus. Since normal interrupts include the interrupt vector, the applications processor does not have to generate an interrupt acknowledge transaction to acquire the vector.
The system also incorporates advanced features of interrupt buffering and interrupt throttling. For example, a bridge may buffer interrupt transactions for an applications processor that cannot currently accept an interrupt because, for example, the applications processor is currently processing an interrupt.
Interrupts may originate from external programmable interrupt controllers. In this operating mode, the interrupts may be delivered as external interrupt transactions. The bridge forwards an interrupt acknowledge from the applications processor to the system bus to obtain the interrupt vector.
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Allison Michael S.
Blakely Robert J.
Embry Leo J.
Morrison John A.
Hewlett--Packard Company
Myers Paul R.
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