Apparatus and method for defective column detection for semicond

Details Apparatus and method for defective column detection for semicond Apparatus and method for defective column detection for semicond

1992-02-28

1995-03-21

Beausoliel, Jr., Robert W.

Excavating

371 211, 365201, G11C 2900

Patent

active

054003431

ABSTRACT:
A circuit and method are provided for a pad efficient and speed efficient test of column leakage currents in silicon memory devices. Memory circuits are blocked into memory bit planes associated with individual I/O pins. Adequate testing requires that each column in each bit plane be tested for charge leakage characteristics. Rather than switching between I/O pins to test memory blocks associated with given pins, the switching circuitry is implemented on the silicon and is selectively coupled to the outputs of the bit planes on the chip. A single high voltage analog output pin is provided for test observations. This eliminates the need to ramp the testing system's voltages up and down and avoids the problems of hot switching between I/O pins.

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