Electrical computers and digital data processing systems: input/ – Interrupt processing – Multimode interrupt processing
Reexamination Certificate
1998-01-29
2002-06-25
Courtenay, III, St. John (Department: 2151)
Electrical computers and digital data processing systems: input/
Interrupt processing
Multimode interrupt processing
C709S241000
Reexamination Certificate
active
06412035
ABSTRACT:
TECHNICAL FIELD
This invention relates to personal computer systems. More particularly, the present invention relates to personal computer systems running the Microsoft Windows family of operating systems.
BACKGROUND OF THE INVENTION
Personal computers running the MS-DOS operating system once dominated the market. Such systems usually run on the Intel 8088 series of microprocessors and allow for near instantaneous interrupt service routines (ISR) to be hooked into the system. These interrupt service routines running in this real-mode environment have a near zero latency interval between the occurrence of the hardware interrupt signal and the execution of the interrupt service routine and allow for the personal computer systems to be used in sophisticated real time tasks. With the advent of more powerful microprocessors and their more sophisticated operating systems, this near zero latency interrupt service routine became difficult to implement and became unavailable to the community of real-time developers.
The appearance of the Intel 80386 series of microprocessors which have additional protected modes and virtual memory paging modes precipitated a number of new products designed to exploit this more powerful environment. Quarterdeck Office Systems of Santa Monica, Calif. introduced a virtual machine manager (VMM) to take advantage of these modes, but the most successful introduction was protected mode Windows 3.1. This product has most of the operating system run in a kernel mode which allows greater unprotected access to the personal computer, vis-à-vis a protected mode where most of the applications run and which allows access to only a limited memory and I/O space of the personal computer. At this time technical difficulties arose in accommodating the transition from MS/PC-DOS to the Microsoft Windows environment, and the patents described below were issued for products to help in this area.
U.S. Pat. No. 4,974,159 to Hargrove, et. al. relates to the transition between the different modes of the Intel 80386 series of microprocessors when running MS/PC-DOS or MS Windows, and U.S. Pat. No. 9,459,869 to Spilo supposedly improves on Hargrove's transition mechanism. However, none of these patents addresses the issue of reduction of the response times of interrupt service routines (ISR) for hardware interrupt request lines (IRQs), and none of them use the Windows kernel fault hooking application programmatic interface (API) for hardware interrupts.
The Microsoft Windows family of operating systems provides a highly restrictive method for programmers to install an interrupt service routine. This method imposes a significant latency between the occurrence of the hardware signal causing the interrupt and the execution of the interrupt service routine in that the interrupt service routine (ISR) only runs after the virtual machine manager (VMM), the VPICD.386, and any other system software which is applicable to that particular hardware interrupt request line (IRQ) are loaded and execute.
Please consider the following example of how the Microsoft Windows protected mode operating systems loads in the series of ISRs for interrupt request line
0
(IRQ
0
) at boot time for the personal computer. It is important to note that on personal computers IRQ
0
is always hardwired to a internal programmable timer device which must have register compatibility with an 8254 (Intel Corporation part number) programmable timer integrated circuit. First, the virtual machine manager (VMM) loads and creates ISRs (vectors) for all the interrupt descriptor table entries. The only function performed by these ISRs is to enable interrupts back on. The VMM exports services by providing a programmatic interface which Microsoft defines as fault hooking services, but which could be called interrupt hooking services, to other Microsoft kernel components to hook these VMM ISRs. These services, as the name implies, allows users to provide the programmatic interface an address or vector and have that address or vector called with the VMM ISR executs. However, the Microsoft documentation for third party developers describes these services as only capable of hooking a limited subset of specific software interrupts. Second, the VPICD.386 loads and hooks all of the VMM ISRs which represent IRQ lines connected to the 8259 device. The VPICD.386 then virtualizes the 8259 device. It arbitrates what other devices can hook these IRQs through services it provides to all other kernel components. Third, the VTD.386 loads and uses the VPICD.386 services to hook the interrupt for IRQ
0
. The VTD.386 then virtualizes the internal programmable timer (8254 compatible device) and presents its timer services to other kernel components. One of the services presented by the VTD.386 is the ability to change the minimum interrupt period (MIP). The MIP is the frequency the occurrence of the 8254 interrupt and hence is the frequency at which various operating system scheduling is done. The greater this frequency, the more responsive and timely is the scheduling mechanism. This service of the VTD.386 greatly complicates this invention.
The important point in this background information is that the operating system provides no services for hooking hardware interrupts except those provided by VPICD.386. Hence, the latency of having the interrupt service routine execute through the VMM and the VPICD.386 is imposed on any user ISR. In the case the timer interrupt IRQ
0
, we have the additional latency of the VTD.386 code. This invention describes how to avoid these latencies by inserting an ISR into the chain of execution prior to the VPICD.386 code.
FIG. 1
shows the execution flow of the invention, and this figure can also be used to imagine the flow of an unmodified IRQ
0
interrupt by connecting the VMM IRQ
0
ISR to the VPICD.386 IRQ
0
ISR and thus eliminating the VHKD.386 module.
Dr. Dobb's Sourcebook published a method to overcome this latency in the March/April issue of 1996 as detailed in an article authored by the author of this invention, V. Webber. A provisional patent application serial number 60/037,112 based upon this article was filed by the inventor of this patent application on Feb. 3 1997.
SUMMARY OF THE INVENTION
It is the object of the present invention to provide a fast hardware interrupt handling module which implements an improved method for inserting a hardware interrupt service routines (ISR) into the hierarchy of Microsoft Windows family of operating system modules for protected mode personal computers which creates a fast hardware interrupt service routine.
It is a further object of the present invention to minimize the latency interval from the occurrence of the hardware interrupt signal to the time of the execution of the interrupt service routine code for the fast hardware interrupt service routine.
It is a further object of the present invention to create a methodology for insertion of these fast hardware interrupt service routines so that it can be easily repeated.
It is a further object of the present invention to create a methodology so programmers can instantaneously transfer control from the fast hardware interrupt service routine to their hardware ISRs designed for their unique devices and exploit this environment of low latency. This methodology will allow this to be done with the standard published kernel application programmatic interface (API) of Windows and with this invention. Several modules of this invention use existing standard MS Windows kernel application programmatic interface calls designed to hook software interrupts to actually hook hardware interrupts. This is the first documented use of these function calls for the hardware interrupt hooking purpose.
These and other objectives will become apparent as the invention is described in greater detail.
REFERENCES:
patent: 4779187 (1988-10-01), Letwin
patent: 5027273 (1991-06-01), Letwin
patent: 5414848 (1995-05-01), Sandage et al.
patent: 5530858 (1996-06-01), Stanley et al.
patent: 5694604 (1997-12-01), Reiffin
patent: 5696970
Courtenay III St. John
Nguyen Van H.
Real Time, Inc.
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