Apparatus and method for decreasing the access time to non-cache

Details Apparatus and method for decreasing the access time to non-cache Apparatus and method for decreasing the access time to non-cache

1997-08-28

1999-03-30

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711118, 711119, 711120, 711121, 711122, 711139, 711150, 711151, 711154, 711167, 711168, G06F 1200

Patent

active

058902163

ABSTRACT:
In a computer system, a multi-port bus controller interposed between a CPU, system memory, and an expansion bus detects when a CPU access is to non-cacheable address space and begins a bus cycle to access the data before receiving a "miss" from a cache coupled to the CPU. By detecting non-cacheable address space independently and in parallel with the cache miss determination, the multi-port bus controller saves from one to three clock cycles in each bus cycle that accesses non-cacheable address space.

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