Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-06-27
2006-06-27
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S220000, C370S208000, C370S478000
Reexamination Certificate
active
07069398
ABSTRACT:
An apparatus and method having a de-interleaving memory and a controller is used for de-interleaving interleaved data in a coded orthogonal frequency division multiplexing receiver. The controller generates the correct access addresses of the de-interleaving memory for the data to be de-interleaved, and controls the read and write operations to the de-interleaving memory. The controller comprises an address generator having a plurality of base address generators, and a read/write control circuitry. By using the de-interleaving memory combined with memory address computation for the interleaved data, frequency de-interleaving, block de-interleaving and time de-interleaving are performed in one-stage approach in the COFDM receiver. The memory size is reduced and the circuitry complexity for performing the de-interleaving process is relatively low.
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Feng Chih-Chun
Hung Yung-Hua
Lin Chun-Yu
Industrial Technology Research Institute
Peugh Brian R.
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