Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
1999-04-19
2003-09-23
Wong, Peter (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S261000, C710S306000
Reexamination Certificate
active
06625679
ABSTRACT:
TECHNICAL FIELD
The invention is directed to an apparatus and a method that distributes interrupts. In particular, the invention is directed to an apparatus and a method that distributes interrupts in a computer architecture employing IA-32 processors.
BACKGROUND ART
Multiprocessor computers implement varying levels of symmetry. Master-slave processor computer systems are very asymmetric, whereas in computers designed with higher levels of symmetry, each of the working processors are capable of performing the same functions. In symmetric computers, the working processors share buses, address the same memory and basic input/output system (BIOS) resources, and receive the same array of interrupts.
New advances in computer architecture may be based on Intel® Architecture (IA)-64 technology by including IA-64 input/output. However, these IA-64 components cannot be used with the current IA-32 processors unless a mechanism is provided to bridge the differences between the IA-32 and IA-64 architectures.
SUMMARY OF INVENTION
A system for distributing interrupts includes a number of applications processors that are coupled together by an advanced programmable interrupt controller (APIC) bus and by a processor bus. One or more applications processors can be so coupled. Also coupled to the processor bus is a bridge. The applications processors are IA-32 components and the bridge translates between the IA-32 architecture of the applications processors and the architecture of the system.
The system may include any number of applications processors and bridge processors. The combination of these applications processors and one bridge forms a node. The nodes are coupled together by a system. Each applications processor has a unique address related to a nodeID of the bridge and a further processor ID.
To distribute interrupts, the system uses advanced features to assert, acknowledge and process the interrupts. Interrupts are forced transfers of execution from a currently running program or task to a special program called an interrupt handler. The applications processors can receive interrupts from other applications processors, or from external devices, such as a keyboard, for example. The sources of the interrupt, as well as the operating mode of the system (i.e., DOS or NT) determines some features of the interrupt handling.
In an embodiment, I/O controllers deliver interrupts to the system via interrupt transactions on the system bus. The bridge monitors the system bus and determines when a particular interrupt transaction is directed to an applications processor at the bridge's node. The bridge may accept the interrupt transaction and assert the interrupt pin on the appropriate applications processor. The interrupt pin on the applications processor may be programmed to produce external interrupts as per IA-32 processor specifications. When the applications processor is able to receive the interrupt, the applications processor will return an interrupt acknowledge on the processor bus. The bridge then provides an interrupt vector. With the interrupt vector, the applications processor is able to associate the appropriate interrupt handler.
The interrupt mechanism also incorporates advanced features of interrupt buffering, prioritizig and thresholding. The bridge will buffer interrupt signals for an applications processor that cannot currently accept an interrupt because, for example, the applications processor is currently processing a previous interrupt.
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Allison Michael S.
Embry Leo J.
Morrison John A.
Hewlett--Packard Company
Vo Tim
Wong Peter
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