Television – Format – Including additional information
Reexamination Certificate
1998-10-28
2001-07-24
Eisenzopf, Reinhard J. (Department: 2614)
Television
Format
Including additional information
C348S476000, C348S478000, C348S581000, C348S556000
Reexamination Certificate
active
06266095
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a video signal processing system including a scaler and a vertical blanking interval (VBI) decoder, and more particularly, to a controller for effectively processing scaler data and VBI data using a scaler memory.
2. Description of the Related Art
FIG. 1
is a block diagram of a typical scaler for scaling video signals by a predetermined ratio. First and second line memory units
10
and
12
, each of which has two line memories, receive luminance data Y and chrominance data C to delay at most two lines. A vertical scaler
14
receives luminance data Y, YD and YDD output by the first line memory unit
10
and chrominance data C, CD and CDD output by the second line memory unit
12
, and then vertically scales the received data and performs filtering for extracting effective lines and improving the screen quality. A horizontal scaler
16
receives luminance data YZ and chrominance data CZ output by the vertical scaler
14
, and then horizontally scales the received data to output scaled data YOUT and COUT.
Meanwhile, in a video signal processing system, there are many devices such as a VBI decoder which allows predetermined data to be output during vertical blanking interval (VBI). The VBI decoder outputs serially VBI data such as closed caption data, teletext data and SMPTE time code data etc, through another external pin during VBI. Thus, the additional external pin is required to output and process the VBI data.
A need therefore exists for a scaler memory controller of a video signal processing system including a scaler and VBI decoder, in which active video data is processed in an active interval and vertical blanking data is processed in a vertical blanking interval (VBI), using a scaler memory.
There also exists a need to provide a scaler memory controller of a video signal processing system including a scaler and a VBI decoder, in which active video data and vertical blanking data are time-division read or written from or to the scaler memory.
A further need exists to provide a method for controlling a scaler memory for processing active video data and vertical blanking data using a scaler memory, in a video signal processing system including a scaler and a VBI decoder.
SUMMARY OF THE INVENTION
There is provided a scaler memory controller of a video signal processing system including a scaler having a memory, preferably operating by a first-in first-out (FIFO) method, for receiving active video data to output data scaled by a predetermined ratio through the memory, and a VBI decoder for processing VBI data received during a vertical blanking interval (VBI), comprising: a control signal generator for generating a mode select signal for setting one selected from the group consisting of a normal mode, for reading or writing the active video data from or to the memory, and a VBI mode, for reading or writing the VBI data from or to the memory, and generating a control signal for enabling data to be read or written from or to the memory in each of the modes; a first multiplexer for receiving the active video data and the VBI data, to select one in accordance with the mode select signal and output the selected signal; write control means for receiving the signal output from the first multiplexer, and if the memory write is enabled by the control signal generator, for scaling the active video data by a predetermined ratio during an active video interval to write the scaled active video data to the memory, or writing the VBI data to the memory during a vertical blanking interval (VBI); read control means for reading scaled active video data from the memory by a FIFO method during the active video interval, or reading the VBI data from the memory by a FIFO method during the VBI, and outputting the read data, if the memory read is enabled by the control signal generator.
There is also provided a scaler memory controller of a video signal processing system including a scaler having a memory, preferably operating by a first-in first-out (FIFO) method, for receiving active video data to output data scaled by a predetermined ratio through the memory, and a VBI decoder for processing VBI data received during a vertical blanking interval (VBI), comprising: mode setting means for setting one selected from the group consisting of a normal mode, for reading or writing the active video data from or to the memory, and a VBI mode, for reading or writing the VBI data from or to the memory; a write address generator for generating an address for scaling the active video data during an active video interval by a predetermined ratio to sequentially write the scaled data to the memory, or an address for sequentially writing the VBI data during the VBI to the memory, in accordance with the set mode; and a read address generator generating an address for FIFO, reading the scaled data during the active video interval, or the VBI data during the VBI, from the memory, in accordance with the set mode.
There is further provided a method for controlling a scaler memory of a video signal processing system including a scaler having a memory, preferably operating by a first-in first-out (FIFO) method, for receiving active video data to output data scaled by a predetermined ratio through the memory, and a VBI decoder for processing the VBI data received during a vertical blanking interval (VBI), for processing the active video data and the VBI data through the memory of the scaler, comprising the steps of: during an active video signal interval, scaling the active video data by a predetermined ratio to write the scaled data in the memory, comparing the total number of pixels with the number of effective pixels during the write process to determine a timing point of beginning to read data, and FIFO reading data at the determined read timing point from the memory; and during the VBI, FIFO reading VBI data written during a previous VBI from the memory and writing VBI data to be read during a next VBI to the memory.
REFERENCES:
patent: 4709394 (1987-11-01), Bessler et al.
patent: 5225875 (1993-07-01), Shapiro et al.
patent: 5638467 (1997-06-01), Chua et al.
patent: 5786866 (1998-07-01), Sani et al.
patent: 5907366 (1999-05-01), Farmer et al.
patent: 6118828 (2000-09-01), Schleifer
Eisenzopf Reinhard J.
F. Chau & Associates LLP
Samsung Electronics Co,. Ltd.
Tran Trang U.
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