Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-06-10
2002-06-11
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S154000, C711S167000
Reexamination Certificate
active
06405279
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application relates to and incorporates herein by reference Japanese Patent Application No. 10-189216 filed on Jul. 3, 1998.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and method for controlling rewriting of data into a rewritable nonvolatile memory.
2. Description of Related Art
Electronic control apparatuses are known, which have a function of rewriting data into a rewritable nonvolatile memory through communications with an externally connected memory rewriting device. In one type, received data is rewritten as writing data at every data receiving. In another type such as disclosed in JP-A-5-189584, each writing data is stored first in a buffer to process a transmission request of all writing data to a memory rewriting device, and then rewriting is executed at a timing when a certain number of data are stored.
In the former type, as shown in
FIG. 8A
, a processing of receiving data
1
,
2
,
3
, etc. from the memory rewriting device and a processing of rewriting those data as writing data
1
,
2
,
3
, etc. are executed separately in alternation with respect to time. The sum of data receiving processing time period and data rewriting processing time period becomes a total processing time period required for an entire data rewriting operation. Further, as shown in
FIG. 8B
, the receiving processing of a plurality of data
1
,
2
,
3
, etc. and the rewriting processing of writing those data as the writing data
1
,
2
,
3
, etc. are executed separately in alternation with respect to time. In this instance also, the sum of the receiving processing time period and the rewriting processing time period becomes a total processing time period required for an entire rewriting operation.
That is, the conventional processing of rewriting of data into a rewritable nonvolatile memory, for instance a flash ROM, is executed as shown in FIG.
9
.
More specifically, at step S
1
in
FIG. 9
, it is checked whether a received data exists in a buffer. If the check result at step S
1
is NO, the processing proceeds to step S
2
only after waiting until a data is received. At step S
2
, a communication interruption command is transmitted to the memory rewriting device because a data can not be received from the memory rewriting device during the execution of data rewriting processing. At next step S
3
, writing of the received data into the flash ROM is started as shown in FIG.
10
. At next step S
4
, the processing does not proceed until a completion of data writing when the data writing into the flash ROM is being executed as shown in FIG.
10
.
Then at step S
5
, a verification of the written data is executed to confirm the completion of writing of data into the flash ROM as shown in FIG.
10
. It is checked whether the verification result is indicative of completion of writing the received data. This verification is executed to check correctness of the data written into a medium by reading out from the flash ROM the data written into the flash ROM and comparing those with the received data stored in the buffer. If the check result at step S
5
is NO, that is, the verification result is not indicative of completion of writing the received data, the processing returns to step S
2
so that the above processing may be repeated in the similar manner.
If the check result at step S
5
is YES, that is the verification result of the written data is OK, it is determined that the writing into the flash ROM has been completed and the processing proceeds to step S
6
. At step S
6
, a communication restart command is transmitted to the memory rewriting device to enable receiving of further data from the memory rewriting device. At next step S
7
, it is checked whether writing of all writing data has been completed. If the check result at step S
7
is NO, that is, the writing of all writing data has not been completed yet, the processing returns to step S
1
, so that the above processing may be repeated in the similar manner. If the check result at step S
700
is YES, that is, the writing of all data has been completed, a request for calculating a check sum of the rewritten data is issued without fail. The completion of writing all writing data is determined based on this request, thus ending this routine.
In the above flash ROM writing wait time period at step S
4
, as shown in
FIG. 10
, the processing is in a wait condition. During this time period, no actual processing is executed because of loop processing and the like. Further, it is unavoidable to interrupt temporarily the communication with the memory rewriting device, because data from the memory rewriting device can not be received during the execution of the data writing processing. As a result, it is impossible to shorten the sum of receiving processing time period and the rewriting processing time period.
SUMMARY OF THE INVENTION
The present invention has an object to obviate the above disadvantage.
The present invention has another object to provide an apparatus and method which is capable of shortening a total time period of a processing of receiving data from an outside and a processing of rewriting of received data into a rewritable nonvolatile memory.
According to the present invention, a receiving processing of storing data received from an outside in a first storage area and a processing of storing the received data in a second storage area as writing data and writing those into a rewritable nonvolatile memory are executed in parallel. Thus, a total time period of the processing of receiving the data from the outside and the processing of rewriting those into the rewritable nonvolatile memory can be shortened.
Preferably, the first storage area is provided by a rotating type buffer. Therefore, even if a number of data are stored in the first storage area in excess of an allowable size, it is not necessitated to shift the remaining data to its top in the first storage area.
More preferably, the first storage area and the second storage area are provided separately by a receiving data buffer and a writing data buffer. By using those buffers alternately at every rewriting operation, the, processing of receiving data from the outside and the processing of rewriting the received data into the rewritable nonvolatile memory can be executed at the same time.
REFERENCES:
patent: 5193153 (1993-03-01), Soutoul
patent: 5386553 (1995-01-01), Fujita
patent: 5671445 (1997-09-01), Gluyas
patent: 5809521 (1998-09-01), Steinmetz
patent: 5-189584 (1993-07-01), None
Komori Hirokazu
Kondo Haruhiko
Chace Christian P.
Denso Corporation
Kim Matthew
Nixon & Vanderhye PC
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