Apparatus and method for controlling memory backup using main po

Details Apparatus and method for controlling memory backup using main po Apparatus and method for controlling memory backup using main po

1999-06-01

2000-07-04

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Data refresh

365228, G11C 700

Patent

active

060848138

ABSTRACT:
In a system using a clock synchronous type synchronous DRAM (SDRAM), when a power supply voltage monitoring circuit informs a timing circuit of a decrease in voltage from a main power supply, the timing circuit outputs a self refresh request signal to a CPU. In response to the self refresh request signal, the CPU outputs a clock enable signal synchronous with the system clock, and a self refresh transfer command signal, which is expressed by a combination of states of memory access control signals, to the SDRAM, so as to start up self refresh of the SDRAM. After the self refresh has been started up, the CPU outputs a clock enable mask signal that masks the clock enable signal to switch a clock enable signal to be supplied to the SDRAM from the clock enable signal output from the CPU to a voltage detection signal of a backup power supply. A reset signal then outputs a reset signal to transfer to backup operation.

REFERENCES:
patent: 5495452 (1996-02-01), Cha
patent: 5712825 (1998-01-01), Hadderman et al.
patent: 5867438 (1999-02-01), Nomura et al.

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