Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2005-04-26
2009-12-22
Tsai, Henry W. H. (Department: 2184)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S233000, C711S118000, C711S133000
Reexamination Certificate
active
07636837
ABSTRACT:
An apparatus includes a branch instruction prediction unit configured to make branch prediction, and a branch prediction control unit configured to control an instruction fetch control unit, an instruction buffer, an instruction decoder, and the branch instruction prediction unit, wherein when the branch prediction control unit ascertains that the branch prediction by the branch instruction prediction unit is erroneous, the branch prediction control unit outputs to the instruction fetch control unit a signal for suppressing an instruction fetch request already supplied to the memory unit and outputs to the instruction buffer a signal for nullifying the instruction buffer during a period between a point in time at which the ascertainment is made by the branch prediction control unit that the branch prediction by the branch instruction prediction unit is erroneous and a point in time at which the instruction buffer fetches a correct instruction from the memory unit.
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Inoue Aiichirou
Sunayama Ryuichi
Ukai Masaki
Fujitsu Limited
Staas & Halsey , LLP
Tsai Henry W. H.
Tseng Cheng-Yuan
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