Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
1999-10-28
2001-04-10
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S233100
Reexamination Certificate
active
06215710
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a double data rate (DDR) synchronous dynamic random access memory (SDRAM) and, more particularly, to an apparatus and method for controlling a data strobe signal at reading data of a DDR SDRAM.
DESCRIPTION OF THE PRIOR ART
Generally, a conventional SDRAM synchronized by an external system clock is employed as a semiconductor memory device to improve operation speed. A conventional SDRAM employs a rising edge of a clock, while a DDR SDRAM employs rising and falling edges of the clock. Accordingly, since the DDR SDRAM can implement high operation speed, the DDR SDRAM is known as a next generation DRAM. The conventional DDR SDRAM uses a data strobe signal to minimize time skew caused between memory chips of a memory chip set at read operation.
Referring to
FIG. 1
, there is shown a timing diagram at reading data of a DDR SDRAM in accordance with the prior art. At first, a glossary of “column address strobe (CAS) latency value” is defined as the number of clocks needed until data is issued at a point of time when a read command has issued. Also, a glossary of “burst length value” is defined as the number of consecutive data. As shown, the CAS latency value is 2 and the burst length value is 4. When data of the DDR SDRAM is read, the data should be issued at the rising and falling edges in response to an enable state of a data strobe signal DQS.
In order that the two consecutive data may be issued, the data strobe signal DQS has a high impedance status HI-Z, which is related to a level between high and low signal levels. When the data strobe signal DQS is low one clock before the data is issued, it is defined as a preamble section. When the data is issued, the data should be synchronized with edges of the data strobe signal DQS. When the data strobe signal DQS is low half clock before the data issue is complete, it is defined as a postamble section. The data strobe signal DQS is controlled so that the preamble and postamble sections of the data strobe signal DQS are set.
Referring
FIG. 2
, there is shown another timing diagram illustrating a conventional method for controlling a data strobe signal. In case where the CAS latency value is 2 and the burst length value is 2, two data are consecutively issued two clocks after a read command RD
1
is issued. Typically, the data strobe signal DQS is controlled by a data strobe enable signal QS_ENABLE. However, when a read command RD
2
is issued two clocks after the read command RD
1
is issued, the postamble and preamble sections A and B of the data strobe signal DQS are consecutive. At this time, the data strobe enable signal QS_ENABLE has a section C, which is activated from a falling edge to a rising edge. If the time of the section C is short, the rising edge of the section C is not detected. Accordingly, since the rising edge of the section C may be not detected, the preamble section disappears. In order that the rising edge of the section C may be detected, a point of time when the data strobe enable signal QS_ENABLE is inactivated from a high signal to a low signal must become earlier. Otherwise, a point of time when the data strobe enable signal QS_ENABLE is activated from a low signal to a high signal must become later. When the point of time inactivated from the high signal to the low signal becomes earlier, the postamble section is influenced. Also, when the point of time activated from the low signal to the high signal becomes later, the preamble section is influenced.
As a result, since the conventional method for controlling the data strobe signal by using only one control signal does not correctly set the preamble and postamble sections, data of the DDR SDRAM may not be read.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an apparatus for controlling a data strobe signal at reading data of a DDR SDRAM by using two control signals.
It is, therefore, another object of the present invention to provide a method for controlling a data strobe signal at reading data of a DDR SDRAM by using two control signals.
In accordance with one aspect of the present invention, there is provided a method for controlling a data strobe signal having preamble and postamble sections in a double data rate (DDR) synchronous dynamic random access memory (SDRAM), wherein the preamble section is a low signal section of the data strobe signal one clock before data is issued and wherein the postamble section is a low signal section of the data strobe signal half clock before the data issue is complete in a data issue section, comprising the steps of: controlling a high impedance status of the data strobe signal at sections, except for the data issue section, the preamble section and the postamble section, in response to a first control signal, wherein the high impedance status is related to a level between high and low signal levels; and controlling a point of time when the preamble section of the data strobe signal begins in response to a second control signal.
In accordance with another aspect of the present invention, there is provided an apparatus for controlling a data strobe signal of a double data rate (DDR) synchronous dynamic random access memory (SDRAM), comprising: a first control signal generator for receiving CAS latency signals containing a CAS latency value, respectively, and output enable signals, wherein the CAS latency value is defined as the number of clocks needed until data is issued at a point of time when a read command is issued; selecting an output enable signal delayed by the predetermined number of clocks, wherein the predetermined number of clocks is less one clock than the CAS latency value of a CAS latency signal at a point of time when a read command is activated; and generating a first control signal identical to the selected output enable signal; a second control signal generator for generating a second control signal activated when the selected output enable signal is activated; and generating the second control signal inactivated in response to a rising or falling delay lock loop signal selected by the CAS latency signal, while the first control signal is inactivated; and an initialization means for initializing the second control signal.
REFERENCES:
patent: 6061292 (2000-05-01), Su et al.
Chu Shin-Ho
Han Jong-Hee
Hyundai Electronics Industries Co,. Ltd.
Jacobson Price Holman & Stern PLLC
Le Vu A.
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