Apparatus and method for controlling address conversion buffer

Details Apparatus and method for controlling address conversion buffer Apparatus and method for controlling address conversion buffer

2008-05-27

2008-05-27

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S209000, C718S108000

Reexamination Certificate

active

10986041

ABSTRACT:
A method for controlling an address conversion buffer, constituted on a processor capable of executing a plurality of threads simultaneously on one core, includes registering address conversion information in an entry of the address conversion buffer that includes a first memory area usable by one of the threads and a second memory area shared among all the threads, allocating a part of the second memory area as a swap area of the first memory area, and transferring data in the swap area to the first memory area, based on thread switching executed by the processor.

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patent: 6718494 (2004-04-01), Jamil et al.
patent: 2003/0191927 (2003-10-01), Joy et al.
patent: 3-22057 (1991-01-01), None
patent: 06-259329 (1994-09-01), None

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