Apparatus and method for controlling address conversion buffer

Details Apparatus and method for controlling address conversion buffer Apparatus and method for controlling address conversion buffer

2008-05-27

2008-05-27

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S209000, C718S108000

Reexamination Certificate

active

07380097

ABSTRACT:
A method for controlling an address conversion buffer, constituted on a processor capable of executing a plurality of threads simultaneously on one core, includes registering address conversion information in an entry of the address conversion buffer that includes a first memory area usable by one of the threads and a second memory area shared among all the threads, allocating a part of the second memory area as a swap area of the first memory area, and transferring data in the swap area to the first memory area, based on thread switching executed by the processor.

REFERENCES:
patent: 4727482 (1988-02-01), Roshon-Larsen et al.
patent: 5640533 (1997-06-01), Hays et al.
patent: 6718494 (2004-04-01), Jamil et al.
patent: 2003/0191927 (2003-10-01), Joy et al.
patent: 3-22057 (1991-01-01), None
patent: 06-259329 (1994-09-01), None

Affiliated with

Also associated with

Rating

Apparatus and method for controlling address conversion buffer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus and method for controlling address conversion buffer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for controlling address conversion buffer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2764616