Apparatus and method for controlling a master/slave system...

Details Apparatus and method for controlling a master/slave system... Apparatus and method for controlling a master/slave system...

2004-10-11

2008-12-16

Kim, Kevin (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S354000

Reexamination Certificate

active

07466784

ABSTRACT:
A method of operating a master/slave system includes the step of identifying a master receive data phase value to coordinate the transfer of data from a slave device without phase alignment circuitry to a master device with a universal phase aligner. Data is transferred from the slave device to the master device in accordance with the master receive data phase value. The master device characterizes a master transmit data phase value to coordinate the transfer of data from the master device to the slave device. Subsequently, the master device routes data to the slave device in accordance with the master transmit data phase value.

REFERENCES:
patent: 4481625 (1984-11-01), Roberts et al.
patent: 5097489 (1992-03-01), Tucci
patent: 5432823 (1995-07-01), Gasbarro et al.
patent: 5485490 (1996-01-01), Leung et al.
patent: 5513327 (1996-04-01), Farmwald et al.
patent: 5554945 (1996-09-01), Lee et al.
patent: 5577236 (1996-11-01), Johnson et al.
patent: 5579352 (1996-11-01), Llewellyn
patent: 5614855 (1997-03-01), Lee et al.
patent: 5615358 (1997-03-01), Vogley
patent: 5692165 (1997-11-01), Jeddeloh et al.
patent: 5757786 (1998-05-01), Joo
patent: 5852640 (1998-12-01), Kliza et al.
patent: 5889824 (1999-03-01), Ueda
patent: 6016282 (2000-01-01), Keeth
patent: 6125419 (2000-09-01), Umemura et al.
patent: 6131149 (2000-10-01), Lu et al.
patent: 6232806 (2001-05-01), Woeste et al.
patent: 6236623 (2001-05-01), Read et al.
patent: 6292903 (2001-09-01), Coteus et al.
patent: 6426984 (2002-07-01), Perino et al.
patent: 6510503 (2003-01-01), Gillingham et al.
patent: 6553472 (2003-04-01), Yang et al.
patent: 6611905 (2003-08-01), Grundon et al.
patent: 6804764 (2004-10-01), LaBerge et al.
patent: 6807614 (2004-10-01), Chung
patent: 6928571 (2005-08-01), Bonella et al.
patent: 6970988 (2005-11-01), Chung
patent: 7076745 (2006-07-01), Togo
patent: 7100066 (2006-08-01), Jeong
patent: 7224595 (2007-05-01), Dreps et al.
patent: 2001/0047450 (2001-11-01), Gillingham et al.
patent: 63276935 (1988-11-01), None
patent: 387907 (1991-04-01), None
patent: 4117709 (1992-04-01), None
K.Y. Chang, “Design of a CMOS Asymmetric Serial Link,” Ph.D. Dissertation, Stanford University, Aug. 1999.
Chang, et al., “A 2Gb/s/pin CMOS Asymmetric Serial Link,” 1998 Symposium on VLSI Circuits Digest of Technical Papers.
Sidiropoulos, S., “A Semidigital Dual Delay-Locked Loop,” IEEE J. Solid State Circuits, vol. 32, No. 11, Nov. 1997.

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