Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
1999-11-05
2001-07-17
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S041000
Reexamination Certificate
active
06262594
ABSTRACT:
BACKGROUND
Systems are normally implemented by mounting a number of discrete components on a printed circuit board. However, implementing the circuitry of discrete components in a single integrated circuit chip yields advantages of cost reduction, low power consumption, space savings and ruggedness. Such a single chip (also called “system-on-chip” and abbreviated as “SOC”)
1
(see
FIG. 1A
) has a number of functional modules
2
-
9
that provide functions different from each other, and may include, for example, a central processing unit (CPU) module
2
, a random access memory (RAM) module
3
, and a liquid crystal display (LCD) module
4
. See page 85 of Electronic Engineering Times, Mar. 29, 1999(an advertisement). It is well known to permanently couple (i.e. hardwire) functional modules
2
-
9
to a group of predetermined pads
1
A-
1
P (not all pads in
FIG. 1
are labeled) for coupling to external circuitry.
Among the pads (e.g. pads
1
I-
1
N) that are hardwired to CPU module
2
, some pads (e.g. pads
1
I-
1
K) may be used in a multiplexed manner by CPU module
2
. Specifically, Intel 8086 and Zilog Z8000 CPUs provide a 16-bit address/data bus that multiplexes the low-order sixteen address bits with the 16-bit data word. Additionally, the 8086 CPU multiplexes four address bits with four status signals on four separate pads. Also, the Intel 8085 CPU has an 8-bit address/data bus that multiplexes the lower half of a 16-bit address with the 8-bit data byte. See pages 172-173 and 209-212 of the book entitled “Microprocessor System Design Concepts” by Nikitas A. Alexandridis, Computer Science Press, 1984.
Moreover, Purcell et al. (see U.S. Pat. No. 5,379,356) describe a single chip (called “CL950 chip” at column 6, lines 5-9) having at least a processor, a decoder coprocessor, and a motion compensation coprocessor that are connected to a global bus (see column 6, lines 10-13 and lines 17-33). The global bus in turn is coupled via “Pad and FFS” to a memory bus that is external to the single chip (e.g. coupled to DRAM as described at column 6, lines 53-55). Purcell et al. also state that “by looping back the CAS signal on the output pin, this embodiment can monitor the time at which the CAS signal is asserted at the external DRAM. Therefore, the uncertainty as to whether the external DRAM receives the column address is removed . . . ” (column 7, lines 3-8). See also U.S. Pat. No. 5,598,514 for another description of the global bus.
U.S. Pat. No. 5,701,507 describes an integrated circuit having several groups of processors and memories, wherein “each processor . . . has direct communication with each memory . . . via a crossbar link . . . ” (column 3, lines 1-11). Moreover, U.S. Pat. No. 5,742,180 (see
FIG. 1B
) describes a gate array, wherein “nine (3×3) subarrays are connected by associated bidirectional cross bars . . . [c]communication at the edge of the nine subarrays goes off-chip via input/output pads or pins . . . ” (column 6, lines 28-31).
Furthermore, U.S. Pat. No. 5,036,473 describes a “partial crossbar interconnect [in which] the I/O pins of each logic chip are subdivided into proper subsets, using the same division on each logic chip. The pins of each crossbar chip are connected to the same subsets of pins from each and every logic chip. Thus crossbar chip ‘n’ is connected to subset ‘n’ of each logic chip's pins. As many crossbar chips are used as there are subsets, and each crossbar chip has as many pins as the number of pins in the subset times the number of logic chips. Each logic chip/crossbar chip pair is interconnected by as many wires, called paths, as there are pins in each subset”. See column 15, line 63 to column 16, line 6.
SUMMARY OF THE INVENTION
In accordance with the invention, an integrated circuit chip has pads (portions of electrical conductors formed on the chip's surface and normally used for receiving external connections, sometimes called “bond pads”) that are grouped into a number of groups, and also has circuitry to allow functional modules in the chip to share, among each other, use of two or more groups of the pads (also called “external function” groups), for transferring signals (such as data signals and control signals) to/from circuitry external to the chip. Each of the functional modules inside the chip is electrically coupled to and decoupled from an external function group as and when necessary to use the pads for external communications. At any time, only one functional module communicates with pads of a given external function group. Sharing of pads as described herein allows the integrated circuit chip to have fewer total pads than otherwise required for transferring data and control signals to/from external circuitry in the absence of such sharing.
In one embodiment, a first functional module in the chip performs a predetermined function that is different from a second functional module, so that the chip can be configured for use of one of these two functional modules. Such a chip may include additional such functional modules thereby to implement a system-on-chip (SOC). Each functional module in the chip has one or more groups of terminals (also called “internal function” groups) for transferring signals to/from the external function groups. As an important aspect of this particular embodiment, a number T of internal function groups is greater than another number S of external function groups. The number of elements (e.g. terminals or pads) in each group are identical to the number of elements in any other group. Therefore, at any given time, each external function group is coupled to only one internal function group, and a number T-S internal function groups are uncoupled from the external function groups (i.e. not coupled to any pads of the integrated circuit chip). So, at any given time, at least one functional module of the integrated circuit chip is not used or is disabled (e.g. if all T-S internal function groups are part of the disabled functional module) in this embodiment.
In one implementation, the system-on-chip includes a switch having T internal ports and S external ports, and for the above-discussed reasons at least T-S internal ports are left uncoupled by the switch. During normal operation of the system-on-chip, the switch (such as a “crossbar switch”) temporarily couples one or more external ports to a corresponding number of internal ports. However, each internal port is coupled permanently (also referred to as “hardwired”) to an internal function group, and vice versa. Moreover, each external port is hardwired to an external function group and vice versa. In one embodiment, the coupling between each external port and a corresponding external function group does not include any switching circuitry, e.g. may include only bus drivers of the type well known in the art.
In one variant, the temporary couplings inside the switch are changed only on power-up (also called “static” couplings) of the system-on-chip. Such static couplings allow a board designer to use the same chip on different boards (each of which may require a different one of the modules to be coupled to external circuitry) by using different static couplings in the switch depending on the requirements of the different boards. In another variant, the temporary couplings inside the switch can be changed at any time during operation (also called “dynamic” couplings), thereby to allow the system-on-chip to dynamically reconfigure the use of a limited number of external function groups among a larger number of internal function groups.
In addition to the switch, the system-on-chip includes a configuration circuit that indicates to the switch specific couplings to be made among the various ports (e.g. that a first internal port is to be coupled to a second internal port and vice versa). If the specific couplings are static couplings then such couplings can be held in, e.g. an erasable read-only-memory included in the system-on-chip. Such a memory may be programmed with different values of control signals, depending
Alasti Ali
Cheung Gordon Kwok-Lung
ATI International SRL
Skjerven, Morrill, Mac Pherson
Suryadevara Omkar K.
Tokar Michael
Tran Anh Q.
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