Computer graphics processing and selective visual display system – Computer graphics display memory system – First in first out
Reexamination Certificate
1999-10-08
2002-10-15
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
First in first out
C345S581000
Reexamination Certificate
active
06466222
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the computation of graphics attributes in a three-dimensional graphics system, and more specifically to an apparatus and method for computing graphic attributes of multiple pixels for multiple data paths simultaneously.
BACKGROUND OF THE INVENTION
Conventional three-dimensional display system processes graphics or pictures one pixel at one time using one data path. Graphics recessing using single data path usually does not satisfy the requirement of a high performance display that is rich in functionality. Parallel processing for multiple pixels using multiple data paths has become a major trend in the hardware design of a display system.
The drawback of a parallel processing system is that almost every hardware module used in a single data path has to be duplicated for a system having double data paths. The die size of an IC chip designed for parallel processing is, therefore, twice of the IC chip which uses only a single data path theoretically. In practice, the die size is more than doubled because more control circuits are required for the double data paths. Hardware Resource sharing is one of the solutions to overcoming the drawback of a parallel processing system.
There are some interpolation functions that have to be implemented in a three-dimensional graphics display system, for example, color interpolation, texture coordinate interpolation and depth value interpolation. Color interpolation is used to generate the pixel colors during scan conversion of a primitive, such as line or a triangle. By interpolating between the colors of vertices, the pixel colors of a primitive are derived. Interpolation between two vertex colors is often done for line primitive color interpolation, and among three vertex colors for triangle primitive color interpolation.
Similarly, texture coordinate interpolation is used to generate the corresponding texture coordinates, and depth value interpolation is used to generate the corresponding depth values of pixels within a primitive during the scan conversion process. For the purpose of easy explanation, the following description uses the color interpolation function as an example. As for the other interpolation functions, the technique can be easily applied in a similar way.
There are several color attributes that are used in a 3D rendering process. Generally, there are Alpha (&agr;), Red (R), Green (G), Blue (B), Specular Red (S
R
), Specular Green (S
G
) Specular Blue (S
B
) and Fog (F). The alpha value is used for alpha test and alpha blending to generate the effect of transparency or translucency. Red, green and blue are the pixel's color values and are used to combine with texture color.
Specular red, specular green and specular blue are the specular components of a primitive and are used in the specular blending for specular effect. Fog attribute is used in the fog blending module to generate fog effect. For one data path, there are eight attributes that have to be calculated. If it is extended to two data paths, there are 16 attributes to calculate. The cost of the hardware circuit to accomplish two data paths is too expensive if the original design for one data path is simply duplicated.
There is an important similarity between the eight attributes in that they are all generated by similar equations in the form of A*X+B*Y+C. In the equation, X and Y are the coordinate values of an incoming pixel, and A, B and C are the attribute coefficients for each of the eight attributes. That is, an incoming pixel uses the same (X, Y) and different (A, B, C) to generate the eight attributes by using the same equation. Assume that, (A
≢
, B
&agr;
, C
&agr;
) are the alpha attribute coefficients. (A
R
, B
R
, C
R
), (A
G
, B
G
, C
G
) and (A
B
, B
B
, C
B
) are the pixel color attribute coefficients. (A
SR
, B
SR
, C
SR
), (A
SG
B
SG
, C
SG
) and (A
SB
, B
SB
, C
SB
) are the specular color attribute coefficients. (A
F
, B
F
, C
F
) are the fog attribute coefficients. The corresponding equations to calculate the eight attributes are listed below:
A
&agr;
*X+B
&agr;
*Y+C
&agr;
=&agr;
A
R
*X+B
R
*Y+C
R
=R
A
G
*X+B
G
*Y+C
G
=G
A
B
*X+B
B
*Y+C
B
=B
A
SR
*X+B
SR
*Y+C
SR
=S
R
A
SG
*X+B
SG
*Y+C
SG
=S
G
A
SB
*X+B
SB
*Y+C
SB
=S
B
A
F
*X+B
F
Y+C
F
=F
Although the eight equations are similar, the circuit for calculation are not shared in a conventional three-dimensional graphics system because of the performance consideration. That is, there is a constraint on the minimum throughout of one pixel data generated per clock cycle. Therefore, there are eight hardware circuits computing similar equations in the color interpolation module for the case of one data path. For the case of double data paths, the hardware circuits become at least doubled.
FIG. 1
shows a typical block diagram of computing color shading for one data path. Each block of color shading computes the function, A*X+B*Y+C, where X, and Y are the coordinates of a specific pixel; A, B, and C are attribute coefficients. The attributes include color attributes (&agr;, R, G, B), specular color attributes (S
R
, S
G
, S
B
), and fog color attribute (F). Conventionally, to achieve higher performance, eight color shading blocks are needed to compute all the eight attributes simultaneously.
FIG. 2
shows a block diagram of computing color shading using two data paths. There are two sets of attributes that have to be generated for two pixels respectively.
FIG. 2
is a straightforward implementation which simply duplicates the circuit used in FIG.
1
. The color, specular and fog attribute coefficients are sent to both of the two data paths with coordinates (X
0
, Y
0
) and (X
1
, Y
1
). It is obvious that there are sixteen function blocks performing the equation A*X+B*Y+C for different attributes. The design requires many gates and consumes a lot of area in an IC chip. There is a strong need for an economic way to achieve high performance color shading design with a less number of gates.
SUMMARY OF THE INVENTION
This invention has been made to satisfy the need of a high performance design for a three-dimensional graphics engine in a graphics display system. The primary object of the invention is to provide an apparatus and method that can compute several graphic attributes using a time-shared computational hardware. Another object is to provide a pipeline design for outputting the graphic attributes through several data paths.
According to this invention, a computational unit is used to compute the attribute values of a plurality of successive pixels simultaneously in a computational cycle for a desired attribute. The computed attribute values are sent to as a group and buffered in a special FIFO which has at least one output data path. In a next computational cycle, the attribute values of another desired attribute can be computed for the successive pixels using the same computational unit. The computed attribute values are sent as another group to another FIFO which also has the same number of output data paths.
After the attribute values of all desired attributes are computed and available, the buffered attribute values are sent to the output data paths. The attribute values of several pixels can be sent out to the different output data paths simultaneously. Because the design has a pipeline architecture, the computational unit is time shared for computing the attribute values of multiple attributes cycle by cycle and the special FIFO buffer provides a mechanism to buffer the attribute values and then send them out after the other attributes are available for the multiple data paths.
REFERENCES:
patent: 5337410 (1994-08-01), Appel
patent: 5485559 (1996-01-01), Sakaibara et al.
patent: 6072505 (2000-06-01), Piazza et al.
Kao Ming-Tsan
Lin Won-Yih
Silicon Integrated Systems Corp.
Tung Kee M.
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