Apparatus and method for compression based error correction...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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Details

C714S710000, C711S102000, C711S103000, C711S162000

Reexamination Certificate

active

07089447

ABSTRACT:
In a data processing system in which the complete set of op-code signal groups are stored in a ROM unit, a programmable, non-volatile memory unit stores the address signal groups of the set of op-code signal groups currently controlling the operation of the data processing system. In addition, the programmable, non-volatile memory unit has error checking and correction signal groups associated with each op-code signal groups. To retrieve an op-code signal group from the ROM unit, the central processing unit applies a pointer/address signal group to the programmable, non-volatile memory. The op-code address and the error checking and correction signal group at the location specified by the pointer/address signal group is retrieved from the programmable, non-volatile memory unit, subjected to error checking and correction procedures and the resulting address signal groups is applied to the ROM unit. The op-code signal group identified by the address signal group is retrieved and transferred to the central processing unit. A net data compression is achieved by this configuration.

REFERENCES:
patent: 5432802 (1995-07-01), Tsuboi
patent: 5787241 (1998-07-01), Henry et al.
patent: 2004/0230879 (2004-11-01), Crosby
patent: 06052064 (1994-02-01), None
patent: 06119255 (1994-04-01), None
patent: 06303149 (1994-10-01), None
patent: 09311825 (1997-12-01), None

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