Apparatus and method for clock skew adjustment in a...

Details Apparatus and method for clock skew adjustment in a... Apparatus and method for clock skew adjustment in a...

2008-04-22

2008-04-22

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Significant integrated structure, layout, or layout...

C326S041000, C326S093000

Reexamination Certificate

active

07362135

ABSTRACT:
A programmable logic fabric includes configurable logic block (CLB) containing registers and combinatorial logic elements. An input switch matrix distributes incoming signals to CLB inputs or inputs of embedded logic elements including a register clock. A routing network allows a variety of routing paths with distinct delays to be selected to route the CLB outputs to the input switch matrices. Presented clock delay insertion architectures allow a leaf node of dedicated clock network and a register clock input can be alternatively routed through the routing network, thereby allowing for the generation of a variable amount of clock delay. Required clock delay for each register minimizing the clock period is computed by clock skew optimization program. A set of alternative clock routes is generated for each register clock where each route delay is close to the corresponding required delay while satisfying the monotone increasing conditions. Optimal clock route for each register clock can be efficiently selected from the alternative clock routes by an integer monotonic program to reduce the clock period of a custom design implemented in the fabric.

REFERENCES:
patent: 5254886 (1993-10-01), El-Ayat et al.
patent: 5712579 (1998-01-01), Duong et al.

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