Apparatus and method for clock recovery in a communication syste

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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376372, 376219, 370516, H03D 324, H04L 700

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active

058987444

ABSTRACT:
A method for recovering the clock in an ADSL (asymmetric digital subscriber line) communication system at the receiver to match the frequency of the transmitted signal. A digital phase locked loop (DPLL) based clock is used to adjust the frequency of data read accesses from a FIFO (first-in first-out) memory (26) in a transceiver unit. The frequency is adjusted according to a predetermined offset value, where the offset value indicates the relative difference between a read location in the FIFO memory (26) and a write location. The predetermined offset value defines an operating point or nominal data location in the FIFO memory (26). A FIFO phase detector (31) determines and affects the frequency adjustment to maintain the FIFO memory at approximately the operating point. One embodiment provides clock recovery for a received ADSL subchannel and a means to recover a 16 kHz clock for a channel control.

REFERENCES:
patent: 5367545 (1994-11-01), Yamashita et al.
patent: 5402452 (1995-03-01), Powell et al.
patent: 5500874 (1996-03-01), Terrell
patent: 5548624 (1996-08-01), Yoshida
patent: 5596301 (1997-01-01), Rybicki et al.
Alliance for Telecommunications Industry Solutions, "Asymmetric Digital Subscriber Line (ADSL) Metallic Interface", Draft American National Standard for Telecommunications, Network and Customer Installation Interfaces, T1E1.4/94-007R7, pp. i-xii and p. 170.
J. Bellamy, "Digital Telephony", Second Edition; John Wiley & Sons, Inc., Section 7.1.1 through Figure 7.4. (1994).

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