Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-08-17
2001-06-05
An, Meng-Al T. (Department: 2154)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S039000
Reexamination Certificate
active
06243836
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to digital processor devices, and more particularly to a digital processor capable of on-chip real-time non-invasive tracing of the execution of program instructions utilizing a circular buffer.
2. Description of the Related Art
One of the most essential debugging tools used by programmers and software engineers is a program trace which is representative of the stream of instructions executed by a digital processor. By examining the instruction stream that was executed, a user (e.g., a programmer or a software engineer) may determine if the application hardware and software are performing properly. For example, if unintended behavior of the hardware or software is detected, the user may determine what caused the behavior.
The application area addressed by the present invention is that of integrated circuits incorporating digital processors used in embedded systems. An embedded system is one in which the processor does not have the usual interfaces present when developing the software which runs on the system. Frequently, these systems are not general purpose and perform a fixed function. Some typical examples of embedded systems are cellular telephones, printers and disk drives. Unlike a desktop system, such as a personal computer, these systems do not have a keyboard and display to be used to debug and verify the interaction of the software and the hardware. Furthermore, the marketplace for these products frequently demands that they be physically small in size, thin, and lightweight. These demands force the use of small, thin, and fine-pitch integrated circuit packages mounted on densely populated printed circuit boards. Fine-pitch circuits have closely spaced package pins, and, as a result of the small package size, only those pins that are essential to the system's function are present (i.e., a normal pin-out chip). Extra pins which would facilitate the debugging process and, in particular, permit collection of a program trace, are not typically provided on such packages. A package that does provide such extra pins is commonly referred to as a bond-out chip.
A program trace is most commonly obtained by connecting a logic analyzer device to a normal pin-out chip or a special bond-out chip that is connected to the digital processor being debugged. A logic analyzer device may be a logic analyzer or an in-circuit emulator, both of which are well known in the art. The logic analyzer typically records a trace of the signals observable on the pins of either the normal pin-out chip or the bond-out pin-out chip. A typical scenario using a logic analyzer as a debugging tool for a target system would be as follows. The target system processor encounters some error in its operation, such as for example dereferencing a null pointer, and halts its operation. The developer desires to construct a program trace up to the halt of execution of the processor to determine the cause of the problem. The developer will set a trace trigger on the offending memory address, that is, the address where execution halted. The developer will then configure a logic analyzer to collect a program trace until the trigger on the offending memory address fires. The logic analyzer will record the processor cycles in a buffer until the trigger fires. When the trigger has fired and execution has halted, the developer will read out the contents of the logic analyzer's buffer and examine the processor's instruction execution, working backwards from the instruction that performed the offending memory access until the instruction that set the pointer to null is encountered.
In this scenario, the logic analyzer collects the trace in a circular buffer. A circular buffer is a buffer that, once filled, overwrites the oldest entries to record new data. In general, it may be necessary to run the target system for an arbitrary length of time before the error occurs and the trigger fires. This period may be long enough to completely fill the logic analyzer's buffer. Therefore, a circular buffer is used to record the bus cycles so that the developer has a record of bus cycles for some time period before the error occurred. The circular buffer gives the developer the ability to “trace until” the event of interest occurs and then analyze the history of the behavior that led to the event.
However, this approach has several limitations in the area of embedded systems. First, as noted, it is difficult to reliably connect a logic analyzer device to the pins of the thin, fine-pitch packages of densely populated circuit boards commonly used in embedded systems (such as cellular telephones). Second, a logic analyzer device cannot be connected at all unless board space around the chip to be monitored is left empty to accommodate the logic analyzer connector. This requirement directly increases the size of the embedded system. Furthermore, the logic analyzer device can monitor only those signals that are available at the package pins of the chip to be monitored. Frequently, the signals required for a program trace are not available at the package pins of a normal pin-out chip. Thus, collecting a program trace would require either operating the system in a mode which forces internal signals to the package pins, thus sacrificing the system timing, or the use of a bond-out pin-out chip in the embedded system, thus sacrificing small size.
In an effort to overcome the problems associated with using a logic analyzer with an embedded system, several approaches have been developed. One approach, described in commonly assigned U.S. Pat. No. 5,724,505 to Argade et al., which is herein incorporated by reference, provides a compressed program trace by on-chip hardware of a digital processor to an external debug host computer. The compressed trace contains the minimum information necessary for a user to reconstruct a full program trace with reference to the program image corresponding to the trace that was collected.
Trace recording hardware is provided on-chip but external to the processor core of a digital processor having a serial port, such as a Joint Test Access Group (JTAG) port. The JTAG port is a standard port used for testing integrated circuits. This standard has been adopted by the Institute of Electrical and Electronics Engineers, Inc., as is now defined as the IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture, which is incorporated herein by reference. The use of a JTAG port is advantageous because no special bond-out chip or logic analyzer is required. The trace recording hardware receives, via an instruction type line as described below, data indicative of instruction types executed by the processor core and also receives, via an inter-module bus, data indicative of program addresses corresponding to the instruction types received via the instruction type bus. The trace recording hardware includes an address first-in-first-out (FIFO) buffer for storing addresses received by the trace recording hardware, and an instruction type FIFO buffer for storing instruction types received by the trace recording hardware.
The trace recording hardware also includes a trace buffer control capable of identifying at least three pre-defined instruction types, preferably including discontinuity and conditionally executed instructions. Certain program instructions are called discontinuities because their execution requires the processor to discontinue the program's normal sequential instruction stream and direct the program's execution to a different, non-sequential address. These discontinuities include jumps, calls, and events such as hardware interrupts. Conditionally executed instructions include instructions such as “MOV.IFT,” i.e., move if true.
Each of the at least three pre-defined instruction types has an associated coding scheme for its corresponding address information. The trace buffer control analyzes the stream of instruction types and corresponding addresses received from the process
An Meng-Al T.
Chang Jung-won
Dickstein , Shapiro, Morin & Oshinsky, LLP
Lucent Technologies - Inc.
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