Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2011-04-19
2011-04-19
Abraham, Esaw T (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S786000
Reexamination Certificate
active
07930613
ABSTRACT:
An apparatus and method for interleaving systematic bits and parity bits to generate an output sequence that can be transmitted in multi-slot packets from a base station to a remote station in a wireless communication system. The apparatus comprises a memory element and a control element coupled to the memory element, wherein the control element is configured to demultiplex the systematic bits and parity bits into sequences, wherein the systematic bits and parity bits are sequentially distributed among the sequences. The control element is further configured to reorder the sequences based on an index set, to group the sequences into segments and to interleave each of the segments forming matrices having elements. The control element is also configured to modulate the elements of the matrices, and to truncate the modulated elements of each matrix, so as to produce the output sequence which comprises truncated modulating elements from each matrix of the matrices.
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Abraham Esaw T
Diaz Hidalgo Espartaco
Ma Jian
Qualcomm Incorporated
Vu Ken
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