Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
1998-01-23
2001-06-19
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S039000, C326S040000, C326S041000, C327S291000
Reexamination Certificate
active
06249149
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to programmable logic devices that utilize logic array blocks. More particularly, this invention relates to a technique for generating a centralized enabled clock signal that can be used throughout a logic array block.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates a programmable logic device
20
in accordance with the prior art. The programmable logic device
20
includes a set of logic array blocks
22
. Row interconnect circuitry
24
and column interconnect circuitry
26
link the various logic array blocks
22
. Input/output elements
28
positioned at the ends of the row interconnect circuitry
24
and column interconnect circuitry
26
are used for standard input/output operations.
FIG. 2
is a more detailed representation of a logic array block
22
in accordance with the prior art. The logic array block
22
includes a logic element stack
30
, comprising a set of individual logic elements
31
A-
31
H. A logic array block local interconnect circuit
32
routes signals into the logic elements
31
. Column-to-row interconnect lines
34
and column-to-row interconnect logic
36
is used to route output signals from the logic elements
31
to the same or other logical array blocks
22
.
FIG. 3
is a more detailed illustration of a prior art logic element
31
. The logic element
31
includes a look-up table
40
, which receives a set of data input signals. The look-up table
40
is programmed to implement a set of logic that is executed on the input signals. An output signal of the look-up table
40
is eventually routed to a register
42
. The output signal is driven out of the register
42
in response to a clock signal from a clock control logic circuit
44
. The clock control logic circuit
44
receives a set of input signals. Some of the signals are processed by a clear/preset logic circuit
46
, while the other signals are processed by a clock selection multiplexer
48
. The clock selection multiplexer
48
allows the register
42
to be driven by different clock signals. The output of the clock selection multiplexer
48
drives only a single register
42
.
The clock control logic
44
is programmed into each logic element
31
. Thus, in the logic element stack
30
of
FIG. 2
, clock generation circuitry is redundantly reproduced for eight logic elements
31
. If this redundant circuitry could be reduced or eliminated, die space and processing costs could be reduced. In addition, inputs to the logic element may be used for combinatorial logic, instead of clock generation operations. Accordingly, it would be highly desirable to provide, from a single circuit, an enabled clock signal for application to all logic element registers within a logic array block of a programmable logic device.
SUMMARY OF THE INVENTION
A logic array block of a programmable logic device includes a clock generation circuit. The clock generation circuit has an input node to receive a clock signal, an enable signal input node to receive an enable signal, a clock generation circuit output node, and a digital logic circuit connected between the clock generation circuit input node, the enable signal input node, and the clock generation circuit output node. The digital logic circuit generates an enabled clock signal on the clock generation circuit output node in response to the clock signal and the enable signal when the enable signal has been asserted during a previous clock state of the clock signal. A set of logic elements, each of which includes a logic element clock input node, is connected to the clock generation circuit output node such that each logic element of the set of logic elements receives the enabled clock signal from the clock generation circuit.
The clock generation circuit provides a logic array block-wide enabled clock signal for each logic element. Thus, unlike the prior art, which locally generates an enabled clock signal at each logic element, the present invention relies upon a single clock generation circuit to provide the same signal to all logic elements. Accordingly, it can be appreciated that the present invention reduces die space and processing costs. Further, the circuit of the invention allows additional input lines to a logic element to be used for combinatorial logic, instead of clock generation operations.
REFERENCES:
patent: 5652529 (1997-07-01), Gould et al.
patent: 5652536 (1997-07-01), Nookala et al.
patent: 5809281 (1998-09-01), Steele et al.
patent: 5811987 (1998-09-01), Ashmore, Jr. et al.
“Quad D-Type Flip-Flop with Clock Enable”, Advanced CMOS Logic Designer's Handbook, Texas Instruments (1987) pp. 2-469 and 2-470.
Altera Corporation
Paik Steven S.
Pennie & Edmonds LLP
Tokar Michael
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