Computer graphics processing and selective visual display system – Computer graphics display memory system – Texture memory
Reexamination Certificate
2000-03-20
2003-06-03
Chauhan, Ulka J. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Texture memory
C345S557000, C345S582000
Reexamination Certificate
active
06573902
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and method of cache memory connection stores image texels, and particularly to an apparatus and method for reducing area occupied and cost of cache memories by a special texture mapping process.
2. Description of the Related Art
Texture mapping is important for a 3D computer graphic processing system because it riches the visual effect of a rendering process. However, the texture mapping process needs to access a lot of texels in a DRAM. If the bandwidth of the DRAM is inadequate, the speed of texture mapping will slow down.
Nowadays in industries, a cache memory is used to resolve the problem of the bandwidth inadequacy when the DRAM is used.
FIG. 1
is a structural diagram of a 3D computer graphic processing system, wherein a 3D graphic engine
11
is a kernel device for executing the rendering process, accesses a DRAM
15
through a DRAM controller
14
and accesses a cache memory
12
through a cache controller
13
. Besides, the speed of the cache memory
12
is much faster than the speed of DRAM
15
. In texture mapping, a pixel accessed by the 3D graphic engine
11
corresponds to a plurality of texels inside the cache memory
12
and DRAM
15
. Firstly, the 3D graphic engine
11
reads the texels stored in the cache memory
12
through the cache controller
13
. The texels correspond to the pixel being displayed. If the texels are not inside the cache memory
12
, the 3D graphic engine
11
reads texels corresponding to the pixel being displayed from the DRAM
15
through the DRAM controller
14
, and saves the texels in the cache memory
12
.
The performance of the cache memory
12
depends on a parameter named hit ratio. The higher the value of the parameter is, the higher the performance of the cache memory
12
is. A well-known method for improving the hit ratio is to increase the quantity of the cache memory
12
, but this method will increase the area occupied and cost of the cache memory
12
.
Besides, there are three main methods of texture mapping. They are a method of selecting nearest point, a method of bilinear filtering and a method of trilinear filtering respectively. The mapping method of selecting the nearest point makes one pixel correspond to one texel. The mapping method of bilinear filtering makes one pixel correspond to four texels, and the attribute value of the pixel is determined by interpolating the attribute values of the four texels. The mapping method of trilinear filtering makes one pixel correspond to eight texels, and the eight texels can be divided into odd layers and even layers. Each of the odd layers and even layers includes four texels to generate a 3D effect. The attribute value of the pixel is determined by interpolating the attribute values of the eight texels when the mapping method of trilinear filtering is used. Currently, the most popular and important method of texture mapping is the mapping method of trilinear filtering because of the reality of the visual effect.
Nowadays in the industries, the eight texels needed by the mapping method of trilinear filtering are obtained from a cache memory having eight data ports to complete eight-texel input or output in one cycle. Generally, the area occupied by a 4M-byte cache memory with eight data ports is about two times of the area occupied by two 2M-byte cache memories with four data ports, or about four times of the area occupied by four 1M-byte cache memories with two data ports. Therefore the cost and area occupied by the prior single cache memory is very large. Besides, the 3D graphic engine
11
usually processes two or more pixels simultaneously in one cycle time to speed up the action of display, or processing two or more textures simultaneously in one cycle time to enhance the visual effect. The prior art in dealing with multiple pixels or multiple textures accessed in one cycle is to use a cache memory
12
with a lot of data ports, and that is not economical enough.
As mentioned above, the current apparatus and method about cache memory connection for texture mapping do not meet the need by the market.
SUMMARY OF THE INVENTION
Accordingly, the object of the present invention is to resolve the drawbacks of large area occupied and large cost in prior art. In order to accomplish the object, the present invention proposes a new cache memory apparatus and method for connecting cache memories for texture mapping. The cache memory apparatus for texture mapping is applied in a computer graphic processing system for storing an array of image texels, which form at least one texture. The cache memory apparatus for texture mapping comprises a plurality of cache memories, each of said cache memories storing a part of the image texels according to the row number of said array of the image texels respectively so as to reduce the area occupied by the cache memories of the computer graphic processing system. Besides, the texels contained in the plurality of cache memories are the same with the texels contained in the prior single cache memory, so the parameter of hit ratio will not be decreased. Furthermore, the texels stored in the cache memory apparatus of the present invention are arranged properly, so there would not be any conflict due to the decrease of data ports of the cache memory apparatus of the present invention. Therefore, the cache memory apparatus of the present invention will complete all texel access in one cycle time. Furthermore, the cache memory apparatus of the present invention can be applied in the well-known mapping method: selecting a nearest point, bilinear filtering and trilinear filtering. When the present invention is used to deal with the mapping methods of selecting the nearest point and bilinear filtering, a plurality of multiplexers are used to reorganize the structure of cache memories in the present invention to increase the utilization efficiency of cache memory apparatus of the present invention. When the present invention is used to deal with the mapping method of accessing one texture and trilinear filtering, the cache memory apparatus proposed for texture mapping comprises the first to fourth cache memories. The first cache memory is used to store the content of odd rows of odd layer of the image texels, the second cache memory is used to store the content of even rows of odd layer of the image texels, the third cache memory is used to store the content of odd rows of even layer of the image texels, and the fourth cache memory is used to store the content of even rows of even layer of the image texels.
The present invention can also be used when the mapping method of multiple textures and multiple pixels are used. When the present invention is used to deal with the mapping method of accessing K textures and trilinear filtering, the apparatus proposed comprises the first to 4K-th cache memories. The first cache memory is used to store the content of odd rows of odd layer of the first texture of the array of the image texels, the second cache memory is used to store the content of even rows of odd layer of the first texture of the array of the image texels, the third cache memory is used to store the content of odd rows of even layer of the first texture of said array of the image texels, and the fourth cache memory is used to store the content of even rows of even layer of the first texture of said array of the image texels. By the same rule, the (4K−3)-th cache memory is used to store the content of odd rows of odd layer of the K-th texture of said array of the image texels, the (4K−2)-th cache memory is used to store the content of even rows of odd layer of the K-th texture of said array of the image texels, the (4K−1)-th cache memory is used to store the content of odd rows of even layer of the K-th texture of said array of the image texels, and the 4K-th cache memory is used to store the content of even rows of even layer of the K-th texture of said array of the image texels, and K is a positive integer which is bigger than one.
Liao Ming-Hao
Pai Hung-Ta
Chauhan Ulka J.
Silicon Integrated Systems Corporation
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