Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
Reexamination Certificate
2000-03-25
2004-11-09
Chung, Phung M. (Department: 2764)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error count or rate
C714S715000, C714S712000
Reexamination Certificate
active
06816987
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the testing of data communications systems and in particular to an apparatus and method for testing data communications systems using built-in self test.
2. Description of the Related Art
Data communications systems are constantly improving in functionality and speed. These systems are also becoming smaller and denser as a result of advances in integrated circuit technology. As integrated circuits are fabricated using increasingly smaller submicron process technologies, multiple subsystems can be combined on a single integrated circuit to produce what is referred to as a System-On-a-Chip or SOC.
As more complex systems, particularly mixed-signal systems, are implemented as SOCs, however, it has become increasingly difficult to test and verify their operation due to several factors. First, the signals generated and used by the various subsystems within a SOC are not readily accessible from outside the integrated circuit, due to the large number of additional pins that would otherwise have to be added to the chip package. Second, the operating frequencies of SOCs, particularly those used in the latest data communications applications, have now reached extremely high speeds, commonly in the GHz range. Third, mixed-signal SOCs, which contain both digital and analog circuitry, require the testing of both the digital and analog characteristics of the signals that they output.
A variety of approaches have been devised to test SOCs. A conventional testing approach is to apply test vectors to, and measure the response from, the SOC through its pins using automated test equipment or ATE. This approach is becoming increasingly impractical because ATEs are having difficulty in keeping up with the continuously increasing speeds of SOCs. In addition, it is difficult for ATEs to adequately test the increasingly complex circuitry of SOCs because the ATE is limited to accessing the internal circuits of an SOC only through its pins. Furthermore, ATEs typically are not capable of testing mixed-signal SOCs because they generally are intended for testing either digital or analog integrated circuits, but not both.
Another testing approach, known as built-in self-test or BIST, includes test circuitry for testing the SOC on the same integrated circuit substrate as the SOC. Consequently, BIST provides an effective way to test the functional operation of SOCs at their full operating speed. However, conventional BIST schemes are primarily intended to test the functionality of digital circuitry and thus do not provide a satisfactory way to verify the exacting timing and voltage specifications (i.e., parametric testing) of the high-speed SOCs used in data communications applications.
In view of the shortcomings of the above-described testing approaches, it is an object of the invention to provide an apparatus and method for testing high-speed data communications systems at their full operating speed.
SUMMARY OF THE INVENTION
The present invention comprises an apparatus and corresponding method for performing a built-in self-test (BIST) of a data communications system. The apparatus of the invention includes a transmitter, a receiver coupled to the transmitter and a test control system coupled to the transmitter and receiver for measuring a data error rate of the data communications system. The transmitter, receiver and test control system are disposed on a common substrate, such as an integrated circuit.
An advantage of the invention is that it enables functional and/or parametric tests to be performed on the transmitter and/or receiver of the data communications system at the full operating speed of the system. Another advantage of the invention is that it allows the data communications circuit to be thoroughly tested in a relatively short amount of time.
These and other features: and advantages of the invention will be better appreciated from the following detailed description of the invention together with the appended drawings.
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Berard Rick
Greig David Vetea
Olson Erlend
Pasqualino Christopher
Broadcom Corporation
Christie Parker & Hale LLP
Chung Phung M.
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