Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-06
2003-05-06
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C327S293000
Reexamination Certificate
active
06560752
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention is directed to an apparatus and method for buffer library selection for use in buffer insertion. In particular, the present invention is directed to an apparatus and method for generating a reduced set of buffers for use during buffer insertion to minimize computational time.
2. Description of Related Art
Buffer insertion has become a critical optimization technique in high performance design. Buffer insertion is used as a means for eliminating long wire connections found in many chip designs, such as Application Specific Integrated Circuit (ASIC) chip designs. An ASIC is a chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. The use of ASICs improve performance over general-purpose CPUs, because ASICs are “hardwired” to do a specific job and do not incur the overhead of fetching and interpreting stored instructions. An ASIC chip performs an electronic operation as fast as it is possible to do so, providing, of course, that the circuit design is efficiently architected.
It has been found that buffers can be used to optimize chip designs by eliminating long wire connections that may cause delay along timing-critical paths. Buffers can be used not only to improve delay along timing-critical paths, but also to sharpen slew rates and fix capacitance and noise violations present in chip designs. Consequently, design automation tools which can effectively and efficiently insert buffers into the chip design are essential to the design environment.
There have been several techniques for buffer insertion proposed. The initially proposed technique by Van Guinean in “Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay,” Intl. Symposium on Circuits and Systems, 1990, pp. 865-868, made use of a single buffer to perform buffer insertion. Since then, various enhancements to this technique have been made.
These enhanced techniques make use of an extensive buffer library B that handles a plurality of buffers and inverting buffers as well. Thus, with these enhanced techniques, rather than passing a single buffer specification into a buffer insertion algorithm, an entire library of buffers is passed to the buffer insertion algorithm. Therefore, using a buffer library instead of a single buffer increases the time complexity and memory usage of the buffer insertion algorithm by a factor of B
2
.
Modern design libraries may contain hundreds of different buffers, which may be both inverting and non-inverting. Not only are several power levels available for each general buffer and inverting buffer, but specialized clock buffers and low voltage gates may be available as well. If a user supplies all possible buffers as input to a buffer insertion algorithm, the algorithm will take several days or weeks to run to completion on a large design if it does not run out of memory first.
Thus, it would be beneficial to have an apparatus and method for selecting a reduced size buffer library for use with a buffer insertion tool such that the reduced size buffer library is of a size that is manageable by a buffer insertion tool, does not require extensive computational time and memory requirements, and adequately reflects the set of buffers in a general buffer library.
SUMMARY OF THE INVENTION
The present invention provides an apparatus and method for buffer selection for use in buffer insertion. With the apparatus and method of the present invention, a design module receives a high-level design specification from a user and generates a chip design based on the high-level design specification. The design specification is input to a buffer insertion tool module which takes the design specification and inserts appropriate buffers into the design to minimize delay along timing-critical paths, sharpen slew rates and fix capacitance and noise violations in the design.
An optimal buffer library generator module operates to reduce a general buffer library down to a optimal buffer library, hereafter referred to as the pruned buffer library, based on parameters that are input to the optimal buffer library generator module. The parameters received by the optimal buffer library generator may include, for example, the range of resistance values and capacitance values to use in a delay model for identifying buffers to include in the pruned buffer library, the type of buffers to include for use with decoupling loads off critical paths, a diameter threshold for buffer cluster, and the like. These parameters may be input automatically from the design module, based on the particular design specification generated, may be input by a user via an input device, or the like.
Based on these parameters, the optimal buffer library generator module selects buffers from the general buffer library for inclusion in a pruned buffer library. The pruned buffer library is then input to the buffer insertion tool module for use in performing the buffer insertion into the design specification obtained from the design module. The result is an optimized design that is output to the data processing system.
In a preferred embodiment of the present invention, the pruned library is generated by generating a set of superior buffers and inverters and clustering the set of superior buffers. A single buffer is then selected from each cluster for inclusion in the pruned library. The result is a smaller buffer library which will provide approximately the same performance during buffer insertion while reducing the amount of computing time and memory requirements.
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Alpert Charles Jay
Gandham Rama Gopal
Neves Jose Luis Pontes Correia
Quay Stephen Thomas
International Business Machines - Corporation
Liu Andrea
Salys Casimer K.
Smith Matthew
Walder, Jr. Stephen J.
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