Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2006-10-30
2010-10-19
Payne, David C (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
Reexamination Certificate
active
07817766
ABSTRACT:
A digital control loop and a method for clock generation. A control loop includes at least one phase detector configured to detect a phase shift of a feedback signal relative to a reference clock signal and output a correction signal on the basis of the phase shift detected. At least one control loop filter is configured to output, on the basis of the correction signal, a first control signal and a second control signal, the first control signal being substantially the same as the second control signal except that oscillations are suppressed in the second control signal. At least one first phase generator is configured to output a first clock signal on the basis of the first control signal and the first phase reference signal, wherein the first clock signal is transmitted at least partially as feedback signal to the phase detector. At least one second phase generator receives the second control signal and the first phase reference signal, wherein the second phase generator is functionally substantially the same as the first phase generator and is configured to output a second clock signal on the basis of the second control signal and the first phase reference signal.
REFERENCES:
patent: 6839860 (2005-01-01), Lin
patent: 6950487 (2005-09-01), Lin et al.
patent: 7046058 (2006-05-01), Fang et al.
patent: 02087086 (2002-10-01), None
Gregorius Peter
Rickes Thomas
Schledz Ralf
Streibl Martin
Panwalkar Vineeta S
Patterson & Sheridan LLP
Payne David C
Qimonda AG
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