Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling
Reexamination Certificate
2003-11-06
2008-11-25
Lee, Thomas (Department: 2195)
Electrical computers and digital processing systems: virtual mac
Task management or control
Process scheduling
C718S100000, C718S105000, C714S030000, C714S037000, C714S039000, C714S045000, C714S047300, C712S225000, C712S226000, C712S227000
Reexamination Certificate
active
07458078
ABSTRACT:
Method and apparatus for tracking thread stacks during a trace of a computer program. Hardware assistance mechanisms allow a processor to autonomically maintain a thread work area for each thread where a call stack is stored. An operating system informs the processor of the size of the data area to allocate to a particular thread work area. When a trace of a computer program is to be performed, trace software, informs the processor to begin maintaining thread call stack information in the thread work area. For each thread in the computer program execution, the processor maintains a work area having a size that is determined based on the size communicated by the operating system. The processor contains microcode to cause the processor to automatically store thread tracking information in the work areas designated by control registers of the processor when a control bit is set.
REFERENCES:
patent: 4291371 (1981-09-01), Holtey
patent: 4598364 (1986-07-01), Gum et al.
patent: 5103394 (1992-04-01), Blasciak
patent: 5438670 (1995-08-01), Baror et al.
patent: 5691920 (1997-11-01), Levine et al.
patent: 5774724 (1998-06-01), Heisch
patent: 5913925 (1999-06-01), Kahle et al.
patent: 5930508 (1999-07-01), Faraboschi et al.
patent: 5937437 (1999-08-01), Roth et al.
patent: 5938778 (1999-08-01), John, Jr. et al.
patent: 5966537 (1999-10-01), Ravichandran
patent: 5987250 (1999-11-01), Subrahmanyam
patent: 6070009 (2000-05-01), Dean et al.
patent: 6098169 (2000-08-01), Ranganathan
patent: 6101524 (2000-08-01), Choi et al.
patent: 6105051 (2000-08-01), Borkenhagen et al.
patent: 6134676 (2000-10-01), VanHuben et al.
patent: 6189141 (2001-02-01), Benitez et al.
patent: 6192513 (2001-02-01), Subrahmanyam
patent: 6206584 (2001-03-01), Hastings
patent: 6223338 (2001-04-01), Smolders
patent: 6237019 (2001-05-01), Ault et al.
patent: 6243804 (2001-06-01), Cheng
patent: 6256775 (2001-07-01), Flynn
patent: 6286132 (2001-09-01), Tanaka et al.
patent: 6324689 (2001-11-01), Lowney et al.
patent: 6330662 (2001-12-01), Patel et al.
patent: 6351844 (2002-02-01), Bala
patent: 6374364 (2002-04-01), McElroy et al.
patent: 6430741 (2002-08-01), Mattson, Jr. et al.
patent: 6442585 (2002-08-01), Dean et al.
patent: 6446029 (2002-09-01), Davidson et al.
patent: 6480938 (2002-11-01), Vondran, Jr.
patent: 6549930 (2003-04-01), Chrysos et al.
patent: 6654781 (2003-11-01), Browning
patent: 6658416 (2003-12-01), Hussain et al.
patent: 6687811 (2004-02-01), Yamada
patent: 6951018 (2005-09-01), Long et al.
patent: 6988186 (2006-01-01), Eickemeyer et al.
patent: 7024668 (2006-04-01), Shiomi et al.
patent: 7207043 (2007-04-01), Blythe et al.
patent: 7237242 (2007-06-01), Blythe et al.
patent: 2001/0014905 (2001-08-01), Onodera
patent: 2001/0032305 (2001-10-01), Barry
patent: 2002/0010733 (2002-01-01), Baba et al.
patent: 2002/0019976 (2002-02-01), Patel et al.
patent: 2002/0124237 (2002-09-01), Sprunt et al.
patent: 2002/0129309 (2002-09-01), Floyd et al.
patent: 2002/0147965 (2002-10-01), Swaine et al.
patent: 2002/0199179 (2002-12-01), Lavery et al.
patent: 2004/0216104 (2004-10-01), Fluhr et al.
patent: 2004/0216105 (2004-10-01), Burky et al.
patent: 2004/0268317 (2004-12-01), Gouriou et al.
patent: 2000029731 (1999-12-01), None
patent: 2000347863 (2000-12-01), None
“Whole-Program Optimization, for Time and Space Efficient Threads”; Dirk Grunwald, Richard Neves; 1996 ACM Publication.
Cohen et al., “Hardware-Assisted Characterization of NAS Benchmarks”, Cluster Computing, vol. 4, No. 3, Jul. 2001, pp. 189-196.
Talla et al., “Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Super Scalar Architectures”, International Conference on Computer Design, Austin, Sep. 17-20, 2000, pp. 163-172.
Iwasawa et al., “Parallelization Method of Fortran DO Loops by Parallelizing Assist System”, Transactions of Information Processings Society of Japan, vol. 36, No. 8, Aug. 1995, pp. 1995-2006.
Talla et al., “Execution Characteristics of Multimedia Applications on a Pentium II Processor”, IEEE International Performance, Computing, and Communications Conference, 19th, Phoenix, Feb. 20-22, 2000, pp. 516-524.
IBM Research Disclosure Bulletin 444188, “Enable Debuggers as an Objective Performanc Measurement Tool for Software Development Cost Reduction”, Apr. 2001, pp. 686-688.
U.S. Appl. No. 09/435,069, Davidson et al., Method and Apparatus for Instruction Sampling for Performance Monitoring and Debug, filed Nov. 4, 1999.
U.S. Appl. No. 08/538,071, Gover et al., Method and System for Selecting and Distinguishing an Event Sequence using an Effective Address in a Proc ssing Syst m, filed Oct. 2, 1995.
DeWitt, Jr. Jimmie Earl
Levine Frank Eliot
Richardson Christopher Michael
Urquhart Robert John
Al Kawsar Abdullah
Glanzman Gerald H.
International Business Machines - Corporation
Lee Thomas
Rodriguez Herman
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