Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-08-18
2001-11-20
Lintz, Paul R. (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06321367
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to the design of integrated circuits. More particularly, this invention relates to a technique for improving the design process for integrated circuits through an automated custom transistor layout system.
BACKGROUND OF THE INVENTION
When designing an integrated circuit, a designer will use various electronic design automation (EDA) tools to describe the elements and functions that will be incorporated into the integrated circuit. For example, the designer may use a hardware description language, such as VHDL. A hardware description language allows the designer to describe the functions that are to be performed by the integrated circuit, without specifying the elements used to perform the functions. Software tools are available to translate the hardware description language into a gate level design that implements the specified functions. Alternatively, the designer may enter the gate level design directly. For example, drawing tools are available for entering gate level designs. Such designs may be represented by a schematic that has symbols to identify each element in a design. In the schematic, every element is represented by a symbol. Generation of the schematic may be accomplished manually or automatically.
In order to fabricate the integrated circuit, the schematic is translated into a physical layout. The physical layout is a description of how the design will be fabricated in the actual device. In other words, it is a physical representation of the elements in the schematic. Generating a physical layout is a time consuming process. Electronic design automation tools exist to generate a physical transistor layout with uniform gates. These types of gates are known as standard cells. However, in the case of non-standard cells, or custom cells, the layout engineer generates the physical transistor layout manually, for instance, by drawing it with a computer. For a typical integrated circuit, it may take months to generate a custom layout.
Thus, it would be highly desirable to improve the integrated circuit design process by providing a tool that can be used to automatically generate physical layouts for custom cells from a circuit schematic.
SUMMARY OF THE INVENTION
A method of automatically generating a custom device layout includes the step of specifying a device type and an associated set of device parameters. The device type is then matched to a selected cell in a cell library. Physical layout regions of the selected cell are then selectively modified in accordance with the device parameters. The physical layout regions may also be selectively modified in accordance with technology design rules in a design rule library. The physical layout regions of the selected cell are then drawn.
The invention provides an automated approach to generating custom transistor layouts. In the prior art, such layouts are generated manually. Thus, the invention reduces design time. The cell library includes a large variety of devices, such as low and medium voltage transistors, high voltage transistors, looped gate transistors, resistors, and other special devices. Thus, the invention is distinct from layout tools that are limited to generating standard transistor cells. In accordance with the invention, the specified transistor may be assigned an arbitrary size, consequently the cell library is not limited by device size.
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Chen Y. Eugene
Chun Perry
Saito Richard C.
Altera Corporation
Garbowski Leigh Marie
Lintz Paul R.
Pennie & Edmonds LLP
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