Apparatus and method for asynchronous dual port FIFO

Details Apparatus and method for asynchronous dual port FIFO Apparatus and method for asynchronous dual port FIFO

1998-09-15

2001-07-17

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C710S057000

Reexamination Certificate

active

06263410

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a first-in-first-out (FIFO) random access memory, and more particularly to an apparatus and method for controlling the access of an asynchronous dual port FIFO memory.
BACKGROUND OF THE INVENTION
The random access memory (RAM) commonly used in an asynchronous FIFO includes dual port random access memories and single port random access memories. Generally speaking, the structure of a dual port RAM provides faster access speed, but the chip size for the structure is bigger. While the access speed of a single port RAM is slower, the chip size is smaller.
FIG. 1
illustrates a conventional asynchronous FIFO consisting of single port RAM banks, input FIFO ports and output FIFO ports.
For designing an asynchronous dual port FIFO, a circuit structure with a “metastable” architecture can be used to synchronize the accessing control signal if the data in the FIFO are accessed one by one. The main circuit in a metastable architecture comprises three D-type flip-flops and is well known to a person skilled in the field. However, in the case of a write frequency f
1
and a read frequency f
2
, a typical metastable architecture can not be used when burst accessing mode is applied in the asynchronous FIFO design if 0.5f
2
<f
1
<f
2
or 0.5f
1
<f
2
<f
1
.
Basically, the problem of controlling an asynchronous FIFO is that in an asynchronous FIFO, different access frequencies may result in uncertainty of addresses specified by the read pointer and the write pointer. It is thus hard to determine if the current FIFO status is full or empty.
FIG. 2
illustrates an asynchronous dual port FIFO in which the Gray code method is used to design the FIFO. The architecture of
FIG. 2
represents one of the most common approaches to solving the problem associated with the unstable memory addresses. This structure reduces the number of bits of an unstable transient state in a read pointer or write pointer to the minimum, while the pointers are being sampled.
In the design of
FIG. 2
, the asynchronous FIFO comprises two Gray code counters. One is used as a read pointer, and the other is used as a write pointer. To determine how much memory space in the FIFO memory can be accessed, the Gray codes corresponding to the read and write pointers are first converted to sequential counts. A subtraction is then performed on the two sequential counts in order to determine the available space in the FIFO.
However, the design in
FIG. 2
has some disadvantages. Because of different access frequencies to an asynchronous FIFO, the relative positions between these two pointers may not actually tell the true use level of the FIFO even with a synchronized circuit implementation. It also requires two status indicator circuits to determine whether the current FIFO status is full or empty.
SUMMARY OF THE INVENTION
This invention has been made to overcome the above mentioned drawbacks in the control of an asynchronous dual port FIFO. It is an object of the present invention to provide an apparatus and method for controlling the access of an asynchronous dual port FIFO accurately and efficiently. It is also an object of the invention to provide an asynchronous dual port FIFO having simple status indicator circuit for determining the current use level of the FIFO.
According to the present invention, a simple sequential counter instead of a Gray code counter is used as the read pointer in an asynchronous dual port FIFO, and the write pointer is a Gray code counter. The write pointer is sampled by a read clock so as to be synchronized with the read pointer. The read pointer is not synchronized to a write clock.
Using a Gray code counter for the write pointer reduces the number of bits in a transient state to a minimum because in such a counter only one bit changes between two adjacent FIFO addresses. The encoding stability is increased. The read pointer is implemented by a typical sequential counter because the encoding circuit of a sequential counter is better than that of a Gray code counter in terms of timing slacks and circuit areas. In addition, a transient state does not occur in the read pointer because it is not synchronized to the write clock.
To determine how much memory space is available for access, the Gray code corresponding to the write pointer is first converted to sequential format by means of a conversion circuit. After performing subtraction on the two sequential counts of write and read pointers, a status indicator comprising two comparators and a 2's complement block outputs an empty signal if the subtraction result is equal to zero.
The subtraction result is also compared with a threshold value to determine if an almost full signal should be issued. The status indicator outputs an almost full signal only if the available memory space is not greater than the threshold value.
The present invention can be applied to an asynchronous FIFO having frequency relationship 0.5f
2
<f
1
<f
2
, where f
2
is the write frequency if f
1
is the read frequency, or via versa. As an example, the circuit design can be used in the asynchronous FIFO between an accelerated graphics port (AGP) and a synchronous graphics random access memory (SGRAM), The AGP typically writes data to the FIFO with a write frequency of 66 MHz and the SGRAM reads data from the FIFO with a read frequency of 100 MHz.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from a careful reading of a detailed description provided herein below, with appropriate reference to the accompanying drawings.


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