Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Reexamination Certificate
1998-06-30
2001-02-06
Pan, Daniel H. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing control
Context preserving (e.g., context swapping, checkpointing,...
C712S223000, C712S231000, C717S152000, C717S152000
Reexamination Certificate
active
06185673
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to the processing of secure computer code that has associated array bounds that limit memory accesses. More particularly, this invention relates to a hardware based technique for array bounds checking through the use of shadow registers.
BACKGROUND OF THE INVENTION
Secure computer code, such as JAVA, from SUN MICROSYSTEMS, INC., Mountain View, California, requires that all accesses to an array be checked to insure that the programmed code does not access prohibited memory spaces. An attempt to access a prohibited memory space must be trapped to insure computer security.
Array bounds checking of computer code can be appreciated with reference to an example associated with the JAVA programming language. Arrays are special types in JAVA. Arrays are used to keep similar information in the same place. Arrays hold a list of objects that can be referenced by indexing. For example, to create an array “a” of ten integers, the following code is used: “int a[]=new int [10]”. Individual variables in the array are referenced by a number, for example, a[0], a[1], through a[9]. Note that the subscripts go from zero, the first element in the array, to the size of the array minus one.
Now suppose that a subsequent source code instruction states: “a[12]=4”. This instruction attempts to load the value “4” into the twelfth position of the array “a”. When the foregoing code is processed by a JAVA compiler, the JAVA compiler will perform a run-time bounds check. This bounds check requires the execution of several instructions. This processing is computationally expensive, especially when the array is in a loop. When the JAVA compiler identifies the foregoing bounds error, it will generate a message and subsequently prohibit processing of the source code.
In view of the foregoing, it would be highly desirable to reduce the array bounds processing burden on a compiler by providing a hardware based technique for array bound checking. Such a technique should be easy to implement. Ideally, such a technique would be controllable through existing software instructions. Thus, the compiler would not be required to process a new class of instructions.
SUMMARY OF THE INVENTION
The apparatus of the invention includes a circuit for processing source code with associated array bounds limitations. The apparatus includes an execution unit that generates a register value signal and an index number signal corresponding to an array value defined in a source code instruction. A primary register is connected to the execution unit. The primary register produces a base memory address signal in response to the register value signal. A shadow register is also connected to the execution unit. The shadow register produces an array bound value signal in response to the register value signal. An address computation circuit is connected to the execution unit and the primary register. The address computation circuit generates an effective memory address signal based upon the base memory address signal and the index number signal. An address comparison circuit generates an array bound error signal when an effective memory address associated with the effective memory address signal exceeds an array bound value associated with the array bound value signal.
The method of the invention includes the step of computing, with an array bounds check circuit, an effective memory address for an array value defined in a source code instruction. An array bound value is then read from a shadow register location defined in the source code instruction. A hardware error signal is then generated when the effective memory address exceeds the array bound value.
The invention reduces the array bounds processing burden on a compiler by providing a hardware based technique for array bounds checking. The technique of the invention can be implemented with well known hardware components. Advantageously, the disclosed technique can be implemented with existing software instructions. Consequently, the compiler is not required to process a new class of instructions.
REFERENCES:
patent: 5384912 (1995-01-01), Ogrinc et al.
patent: 5644709 (1997-07-01), Justin
Galliani William S.
Pan Daniel H.
Pennie & Edmonds LLP
Sun Microsystems Inc.
LandOfFree
Apparatus and method for array bounds checking with a shadow... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for array bounds checking with a shadow..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for array bounds checking with a shadow... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2602293