Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Patent
1997-12-31
1999-12-14
Ray, Gopal C.
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
710109, 710111, G06F 13364, G06F 1318
Patent
active
060031026
ABSTRACT:
Requests from CPU module units are arbitrated according to a two-level priority scheme, the first level being of a higher priority than the second level. The first level includes a specific CPU module unit, and the second level includes a predetermined sequence of values corresponding to the remaining CPU module units. During each arbitration cycle, a request from the first level CPU module is automatically granted. If the first level CPU module unit has not asserted a request, requests from the second level module units are arbitrated according to the above-mentioned predetermined sequence. The sequence value corresponding to the second level CPU module whose request was most recently granted is latched. Arbitration is then granted to the module unit corresponding to the sequence value which follows the latched value. If the corresponding module unit has not asserted a request, then arbitration is granted to the module unit corresponding to the next value in the predetermined sequence, and so on, unit all of the module units assigned to the second priority level are polled. If no requests have been asserted by the second level module units, arbitration defaults to the first level module unit.
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Aggarwal Sandeep
Aybay Gunes
Ray Gopal C.
Sun Microsystems Inc.
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