Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-06-02
2003-04-15
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06549022
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to failure analysis and qualification testing of integrated circuits (ICs), and specifically to an apparatus and method for analyzing and visualizing functional failures in an IC. These functional failures result from timing errors in the IC which lead to errors in output states of the IC. The apparatus and method of the present invention can be used to locate any circuit elements in the IC that are responsible for producing functional failures therein.
BACKGROUND OF THE INVENTION
Functional failures in an integrated circuit (IC) can arise when information traveling along a particular path in the IC (termed herein a critical timing path) is advanced or delayed relative to information traveling along other paths in the IC so that an incorrect value of an output state (i.e. an output voltage) from the IC is produced. Functional failures can be produced by various types of circuit elements including resistive interconnections and switching transistors. An increased resistance in a resistive interconnection can slow down the flow of electricity through that interconnection. Similarly, a delay in a switching transition of a transistor can slow down the flow of an electrical signal being transmitted through that transistor.
The delay in information travel produced by critical timing paths or resistive interconnections is frequency dependent so that over a certain range of clock frequencies, the IC behaves as expected in response to a set of input test vectors since for this range of frequencies the timing error can be accommodated by the IC. However, at higher clock frequencies, the IC can produce an abnormal or inconsistent output in response to the same set of input test vectors. The presence of functional failures in an IC can thus limit the range of clock frequencies over which the IC can be used. Similarly, functional failures can appear in an IC when the IC is operated at a temperature that is too high or too low, or when the operating voltage to the IC is outside a certain range.
An ability to locate any circuit elements which produce or contribute to functional failures is of value since this allows a particular IC to be optimized for speed and accuracy by designing the IC and/or the IC fabrication processes so as to eliminate or minimize critical timing paths or resistive interconnections in the IC, thereby minimizing timing errors in the IC. This can result in an increase in the speed at which the IC can be operated and validated as being free from functional failures. From an economic standpoint, ICs (e.g. computer chips) validated for operation at higher-speeds are of greater value and can gain more market share than lower-speed ICs. Additionally, an ability to locate the circuit elements responsible for producing functional failures in an IC is important for quality control during IC fabrication, for failure analysis of ICs, and for qualification and acceptance testing of ICs.
Heretofore, the analysis of functional failures in ICs has been difficult and time consuming. One method for characterizing critical timing paths and analyzing timing related failure modes in ICs is based on localized photocurrent generation as disclosed in U.S. Pat. No. 4,698,587 to Burns et al. The method of Burns et al is complicated, requiring that the “ON” and “OFF” states of each transistor being tested be completely mapped during each clock cycle. The information thus obtained must then be stored so that it can be used subsequently to perturb operation of each transistor only during times in which the transistor is transitioning from the “ON” state to the “OFF” state. This perturbation is performed using an above-bandgap focused laser beam which induces a leakage photocurrent in the transistor due to photogenerated carriers (i.e. electrons and holes). This leakage photocurrent slows down switching in the transistor, with the transition time required for the transistor to reach the “OFF” state being measured by detecting the induced photocurrent.
What is needed is a method of rapidly measuring functional failures in an IC without the need to first obtain a detailed knowledge of the state of each transistor during each clock cycle. Additionally, a method is needed which allows the identification of circuit elements of whatever type that contribute to timing errors and thereby produce functional failures in an IC. Finally, a method is needed which quickly and directly pinpoints the location of any circuit elements in the IC producing the functional failures without resorting to complicated calculations or analysis.
An advantage of the present invention is that it does not require a detailed knowledge of the state of each transistor in an IC being tested during each clock cycle.
Another advantage of the present invention is that it does not require a photocurrent to be generated in the IC being tested.
A further advantage of the present invention is that it can identify and localize functional failures produced different types of circuit elements, including transistors and resistive interconnections.
Yet another advantage of the present invention is that it can be used to directly and simply form an image or map of the location of any circuit elements in an IC which are responsible for producing functional failures therein.
Still another advantage of the present invention is that it does not measure permanent defects such as open-circuit or short-circuit defects which are unrelated to functional failures and timing errors.
A further advantage of the present invention is that it is nondestructive so that it can be used for qualification testing of ICs without permanently damaging the ICs.
Yet another advantage of the present invention is that it is applicable to the measurement of functional failures in ICs which employ multiple levels of patterned metallization, and to the measurement of functional failures in ICs which are mounted device-side-down in a flip-chip arrangement. The wavelength of a focused laser beam used in the present invention can be selected so that the substrate (e.g. comprising silicon, germanium or a III-V compound semiconductor) whereon the IC is fabricated is sufficiently transmissive to the laser beam so that analysis can be performed through the substrate. This can simplify the analysis since the focused laser beam can access circuit elements (e.g. transistors) of the IC without being blocked by multiple levels of patterned metallization which can overlie the circuit elements.
These and other advantages of the method of the present invention will become evident to those skilled in the art.
SUMMARY OF THE INVENTION
The present invention relates to an apparatus for analyzing an IC to identify at least one circuit element responsible for producing a functional failure in the IC. The apparatus comprises means for operating the IC under conditions wherein the functional failure occurs, with the functional failure producing over time a fraction of defective (i.e. incorrect) output states (i.e. output voltages) and a remainder of good output states at one or more outputs from the IC in response to a set of input test vectors repeatedly provided to the IC; a laser producing a beam having a photon energy that is less than a bandgap energy of a substrate (e.g. a silicon substrate) whereon the IC is formed; means for focusing and scanning the laser beam across the IC, thereby producing localized heating within the IC that generates a change in the fraction of defective output states from the IC, the focusing and scanning means further providing a position signal to indicate the location of the laser beam on the IC at any instant in time; and means, receiving inputs of the position signal and the change in the fraction of defective output states from the IC, for mapping the location of each circuit element within the IC responsible for the change in the fraction of defective output states from the IC. The apparatus of the present invention can be used to locate circuit elements such as transistors (e.g. switching trans
Bruce Michael R.
Bruce Victoria J.
Cole, Jr. Edward I.
Hawkins Charles F.
Ring Rosalinda M.
Cuneo Kamand
Hohimer John P.
Sandia Corporation
Tang Minh N.
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