Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-06-11
2001-02-20
Moise, Emmanuel L. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S719000, C714S025000, C714S037000, C365S201000
Reexamination Certificate
active
06192494
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus and a method for analyzing circuit test results, and further a recording medium storing an analytical program for analyzing the circuit test results, which are suitably used for an LSI having memory cells.
Electrical tests for an LSI having memory cells are carried out by an electric testing device. The subject of the electrical test is the memory cells. Specifically, through the electric testing device, certain test data are written into each memory cell on the LSI and thereafter it is checked whether each written datum can be non-defectively read out therefrom.
There are included both inherently defective memory cells and entirely non-defective memory cells in those memory cells as judged to be defective by the electric testing device. Such a memory cell as to be regarded as defective by the testing device notwithstanding its being indeed non-defective is called a pseudo- defective memory cell hereinafter.
In order to distinguish between an actually defective memory cell and a pseudo-defective memory cell among those as judged to be defective memory cells as above, it is necessary to re-examine each of all memory cells as judged to be defective. Such a re-examination requires a great deal of labor.
An address of the memory cell as judged to be defective is obtained from data of the circuit test results, however, it is far difficult to get hold of where the memory cell is positioned on a wafer.
SUMMARY OF THE INVENTION
Thus, an object of the present invention is to provide a circuit test result analyzing apparatus which can discriminate between a really defective memory cell and a pseudo-defective memory cell and further designate any positions of the really defective memory cells on a wafer.
Another object of the present invention is to provide a method of analyzing the circuit test results, which is suitable for the above circuit test result analyzing apparatus.
A still another object of the present invention is to provide a recording medium storing an analytical program for analyzing the circuit test results.
The circuit test result analyzing apparatus according to the present invention is directed to analyzing the test results of such a circuit as to comprise a primary circuit and a secondary circuit group including a plurality of secondary circuits each having the possibility of functioning defectively under the influence of the primary circuit.
According to an aspect of the present invention, the circuit test result analyzing apparatus comprises a data base section and a defect data separating section for separating defect data. The data base section holds, as information in a combination form between the primary circuit and the secondary circuit group, position information about the primary circuit and the secondary circuit group each disposed on a substrate and interconnection information between the primary circuit and the secondary circuit group. The data base section also judges that the primary circuit causes the defects when all the secondary circuits function defectively in an equal level. The data base section further judges that a specific secondary circuit causes the defects when the specific secondary circuit of the secondary circuit group functions more defectively than any other secondary circuits. The defect data separating section is to separate between one kind of defect data attributable to a circuit causing some defects and the other kind of defect data attributable to a circuit causing no defects, according to the judgments in the data base section.
A method of analyzing the circuit test results according to the present invention is directed to analyzing the circuit test results of the circuit comprising the primary circuit and the secondary circuit group consisting of a plurality of secondary circuits each having the possibility of functioning defectively under the influence of the primary circuit.
According to another aspect of the present invention, the method of analyzing circuit test results comprises a first step of holding, as information in a combination form of the primary circuit and the secondary circuit group, position information about the primary circuit and the secondary circuit group each disposed on a substrate and interconnection information between the primary circuit and the secondary circuit group; a second step of judging that the primary circuit causes the defects when all the secondary circuits function defectively alike, and that a specific secondary circuit causes the defect when the specific secondary circuit functions more defectively than any other secondary circuits; and a third step of separating the defect data between one kind of defect data attributable to a circuit causing some defect and the other kind of defect data attributable to a circuit causing no defect, according to the judgments in the second step.
According to the present invention, it also provides a recording medium storing an analytical program for analyzing the circuit test results of the circuit comprising the primary circuit and the secondary circuit group consisting of a plurality of secondary circuits each having the possibility of functioning defectively under the influence of the primary circuit.
The analytical program for analyzing test results is intended to carry out the following steps: a first step of holding in a computer, as information in a combination form between the primary circuit and the secondary circuit group, position information about the primary circuit and the secondary circuit group each disposed on a substrate and interconnection information between the primary circuit and the secondary circuit group; a second step of judging that the primary circuit causes the defects when all the secondary circuits function defectively alike, and that a specific secondary circuit causes the defective when the specific secondary circuit of the secondary circuit group functions more defectively than any other secondary circuits; and a third step of separating the defect data between one kind of defect data attributable to a causing some defects and the other kind of defect data attributable to a circuit causing no defects according to the judgments in the second step.
REFERENCES:
patent: 5442642 (1995-08-01), Ingalls et al.
patent: 5850404 (1998-12-01), Sanda
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patent: 8-201486 (1996-08-01), None
patent: 9-96662 (1997-04-01), None
patent: 9-179605 (1997-07-01), None
patent: 10-92883 (1998-04-01), None
Foley & Lardner
Moise Emmanuel L.
NEC Corporation
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