Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
2000-09-28
2004-08-17
Tsai, Henry W. H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C712S244000
Reexamination Certificate
active
06779106
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention is directed to an apparatus and method for an enhanced integer divide in an IA64 architecture.
2. Description of Related Art
The combination of instructions required to perform an integer divide in an IA64 architecture provide little opportunity for instruction level parallelism. The standard divide routine has such a degree of inter-instruction dependency that no more than two instructions are ever executed in parallel. Because of this, instruction units are wasting time processing NOPs. Thus, it would be beneficial to have an apparatus and method for performing integer divides in an IA64 architecture which does not waste processing time on NOP instructions.
SUMMARY OF THE INVENTION
The present invention provides an apparatus and method for performing integer divide operations in an IA64 architecture based data processing system. The apparatus and method of the present invention insert integer divide checks in place of NOP instructions in the instruction bundles associated with integer divide operations. The checks serve to identify typically encountered integer divide operations. Based on such identifications, the integer divide operation may be short-circuited such that the appropriate result may be returned without having to complete the integer divide operation.
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Roberts Diana L.
Tsai Henry W. H.
Walder, Jr. Stephen J.
Yee Duke W.
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