Apparatus and method for an adaptive multiple line prefetcher

Details Apparatus and method for an adaptive multiple line prefetcher Apparatus and method for an adaptive multiple line prefetcher

2007-06-05

2007-06-05

Sough, Hyung (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S167000, C711S213000

Reexamination Certificate

active

10611619

ABSTRACT:
A method and apparatus for adaptive multiple line prefetching. In one embodiment, the method includes the identification of a prefetch depth. As described herein, a prefetch depth may refer to a number of memory lines to be prefetched to temporary (cache) memory. Once the prefetch depth is identified, prefetching is performed according to the identified prefetch depth. During the prefetching, the prefetching is adjusted as changes in the prefetch depth are detected. Accordingly, the dynamic adaptive multi-line prefetching mechanism described herein promotes higher system performance by the use of a more efficient prefetching mechanism.

REFERENCES:
patent: 2004/0049641 (2004-03-01), So et al.
patent: 2004/0148470 (2004-07-01), Schulz
patent: 2004/0205298 (2004-10-01), Bearden et al.

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