Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
2001-10-15
2004-03-30
Nguyen, T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S147000, C711S148000, C711S154000, C711S155000, C709S238000, C709S239000, C709S240000, C710S052000, C710S053000, C710S054000, C710S056000, C710S057000
Reexamination Certificate
active
06715055
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer system nodes and, more particularly, to buffer space allocation within those nodes.
2. Description of the Related Art
In a typical computer system, one or more processors may communicate with input/output (I/O) devices over one or more buses. In addition those processors may communicate with each other through an additional bus or buses. In many cases, these buses are shared buses.
Unfortunately, many shared bus systems suffer from drawbacks. For example, multiple devices attached to a bus may present a relatively large electrical capacitance to devices driving signals on the bus. In addition, the multiple attach points on a shared bus produce signal reflections at high signal frequencies which reduce signal integrity. As a result, signal frequencies on the bus are generally kept relatively low in order to maintain signal integrity at an acceptable level. The relatively low signal frequencies reduce signal bandwidth, limiting the performance of devices attached to the bus.
Lack of scalability to larger numbers of devices is another disadvantage of shared bus systems. The available bandwidth of a shared bus is substantially fixed (and may decrease if adding additional devices causes a reduction in signal frequencies upon the bus). Once the bandwidth requirements of the devices attached to the bus (either directly or indirectly) exceeds the available bandwidth of the bus, devices will frequently be stalled when attempting access to the bus, and overall performance of the computer system including the shared bus will most likely be reduced. An example of a shared bus used by many systems is a front side bus (FSB), which may typically interconnect one or more processors and a system controller.
To overcome some of the drawbacks of a shared bus, some computers systems may use packet-based communications between devices or nodes. In such systems, nodes may communicate with each other by exchanging packets of information. In general, a “node” is a device which is capable of participating in transactions upon an interconnect. For example, the interconnect may be packet-based, and the node may be configured to receive and transmit packets. Generally speaking, a “packet” is a communication between two nodes: an initiating or “source” node which transmits the packet and a destination or “target” node which receives the packet. When a packet reaches the target node, the target node accepts the information conveyed by the packet and processes the information internally. A node located on a communication path between the source and target nodes may relay or forward the packet from the source node to the target node.
In some instances, a node may have multiple packet interface circuits. These interface circuits may use buffering mechanisms to buffer a number of different types of pending transactions from a source node to a destination node. However some buffering mechanisms may require large numbers of buffers to handle the different types of transactions. Large numbers of buffers may require significant die area of an integrated circuit chip. Therefore, during design, tradeoffs may sometimes be made between performance and die area.
SUMMARY OF THE INVENTION
Various embodiments of an apparatus and method for allocating buffer space are disclosed. An apparatus is described in which the locations of a buffer are used to store a plurality of control packets received in a node, wherein the plurality of control packets belong to a plurality of virtual channels. The number of locations assigned to each virtual channel may be dynamically allocated. The number of locations allocated to each virtual channel may be determined by an update circuit. Count values corresponding to the number of locations allocated to each virtual channel may then be stored within a programmable storage, such as a register, for example. The count values may be subsequently copied into a slave register and incremented and decremented as locations become available and notifications corresponding to the available locations are sent, respectively.
Broadly speaking, in one embodiment, an apparatus is contemplated which includes a buffer including a plurality of storage locations configured to store a plurality of control packets each belonging to one of a plurality of virtual channels. The apparatus also includes a programmable storage configured to store a plurality of count values. Each of the count values is indicative of a number of the storage locations allocated to a respective one of the plurality of virtual channels. Further, the apparatus includes an update circuit configured to write the plurality of count values to the programmable storage.
In one specific implementation, the update circuit may be further configured to determine the number of the plurality of locations to allocate to each of the plurality of virtual channels. Further, the apparatus may include a control circuit coupled to the programmable storage. The control circuit may be configured to cause a plurality of default count values to be stored within the programmable storage in response to detecting a cold reset. The default count values are dependent upon a type of communication link coupled between a source and the apparatus.
In another specific implementation, the apparatus includes a slave storage coupled to the programmable storage and configured to store a copy of the plurality of count values in a second plurality of locations. Each of said second plurality of locations may be configured to be incremented and decremented during use. The control circuit may be configured to increment a given location of the second plurality of locations in response to a corresponding location within the buffer becoming available. The control unit may be further configured to decrement the given location of the second plurality of locations in response to a notification of the corresponding available location being sent.
In another embodiment, a method of allocating locations within a buffer is contemplated. The method includes storing a plurality of control packets in a plurality of storage locations. Each of the plurality of control packets belongs to one of a plurality of virtual channels. The method also includes determining a number of the plurality of locations to allocate to each of the plurality of virtual channels. Further, the method includes allocating the plurality of storage locations by storing a plurality of count values within a programmable storage. Each of the count values may be indicative of the number of said plurality of storage locations allocated to a respective one of the plurality of virtual channels.
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Curran Stephen J.
Merkel Lawrence J.
Nguyen T.
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