Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus expansion or extension
Reexamination Certificate
2006-12-05
2006-12-05
Perveen, Rehana (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus expansion or extension
C710S305000, C710S304000, C711S111000, C714S100000
Reexamination Certificate
active
07146448
ABSTRACT:
A storage controller configured to adopt orphaned I/O ports is disclosed. The controller includes multiple field-replaceable units (FRUs) that plug into a backplane having local buses. At least two of the FRUs have microprocessors and memory for processing I/O requests received from host computers for accessing storage devices controlled by the controller. Other of the FRUs include I/O ports for receiving the requests from the hosts and bus bridges for bridging the I/O ports to the backplane local buses in such a manner that if one of the processing FRUs fails, the surviving processing FRU detects the failure and responsively adopts the I/O ports previously serviced by the failed FRU to service the subsequently received I/O requests on the adopted I/O ports. The I/O port FRUs also include I/O ports for transferring data with the storage devices that are also adopted by the surviving processing FRU.
REFERENCES:
patent: 4217486 (1980-08-01), Tawfik et al.
patent: 4428044 (1984-01-01), Liron
patent: 5345565 (1994-09-01), Jibbe et al.
patent: 5483528 (1996-01-01), Christensen
patent: 5530842 (1996-06-01), Abraham et al.
patent: 5619642 (1997-04-01), Nielson et al.
patent: 5668956 (1997-09-01), Okazawa et al.
patent: 5680579 (1997-10-01), Young et al.
patent: 5812754 (1998-09-01), Lui et al.
patent: 5881254 (1999-03-01), Corrigan et al.
patent: 6038680 (2000-03-01), Olarig
patent: 6094699 (2000-07-01), Surugucchi et al.
patent: 6098140 (2000-08-01), Pecone et al.
patent: 6185652 (2001-02-01), Shek et al.
patent: 6243829 (2001-06-01), Chan
patent: 6272533 (2001-08-01), Browne
patent: 6397293 (2002-05-01), Shrader et al.
patent: 6421769 (2002-07-01), Teitenberg et al.
patent: 6470429 (2002-10-01), Jones et al.
patent: 6493795 (2002-12-01), Arsenault et al.
patent: 6502157 (2002-12-01), Batchelor et al.
patent: 6507581 (2003-01-01), Sgammato
patent: 6629179 (2003-09-01), Bashford
patent: 6718408 (2004-04-01), Esterberg et al.
patent: 6839788 (2005-01-01), Pecone
patent: 7069368 (2006-06-01), Thornton
patent: 2001/0013076 (2001-08-01), Yamamoto
patent: 2002/0029319 (2002-03-01), Robbins et al.
patent: 2002/0069317 (2002-06-01), Chow et al.
patent: 2002/0069334 (2002-06-01), Hsia et al.
patent: 2002/0083111 (2002-06-01), Row et al.
patent: 2002/0091828 (2002-07-01), Kitamura et al.
patent: 2002/0099881 (2002-07-01), Gugel
patent: 2002/0194412 (2002-12-01), Bottom
patent: 2003/0065733 (2003-04-01), Pecone
patent: 2003/0065836 (2003-04-01), Pecone
patent: 2004/0177126 (2004-09-01), Maine
patent: 2005/0102557 (2005-05-01), Davies et al.
patent: 0800138 (1997-10-01), None
patent: 0817054 (1998-01-01), None
patent: 2396726 (2004-06-01), None
patent: 2001142648 (2001-05-01), None
“A high I/O reconfigurable crossbar switch” by Young, S.; Alfke, P.; Fewer, C.; McMillan, S.; Blodget, B.; Levi, D. (abstract only.
“Activity-sensitive architectural power analysis” by Landman, P.E.; Rabaey, J.M. (abstract only).
Young et al; “A High I/O Reconfigurable Crossbar Switch”;Field-Programmable Custom Computing Machines, 2003. FCCM 2003. 11thAnnual IEEE Symposium; Apr. 9-11, 2003; pp.x +312.
Landman et al; “Activity-Sensitive Architectural Power Analysis”;Computer-Aided Design of Integrated Circuites and Systems, IEEE Transactions; Jun. 1996; pp. 571-587.
U.S. Office Action for U.S. Appl. No. 09/967,027, Examiner G. Ray, Apr. 30, 2004, pp. 1-7 and cover sheet.
U.S. Office Action for U.S. Appl. No. 09/967,126, Examiner T. Vo, Mar. 7, 2005, pp. 1-5 and cover sheet.
European Examination Report for Application No. GB0406742.7, dated Nov. 10, 2004.
European Examination Report for Application No. GB0406739.3, dated Nov. 10, 2004.
European Examination Report for Application No. GB0406740.1, dated Nov. 10, 2004.
DCM Presentation. DCM Technologies, 39675 Cedar Blvd. #220, Newark, CA 94560.
“PEX 8114: PCI-X -PCI Express Bridge,” Data Book. Version 0.70. May 2004. PLX Technology, Inc.
“Corex-V10 PCI-X Initiator/Target” Datasheet #2. DCM Technologies, 39675 Cedar Blvd., #220, Newark, CA 94560.
“DCM Corex-V10 FAQ.” version 1.00. DCM Technologies, 39675 Cedar Blvd., #220, Newark, CA 94560.
IDT. “24-lane 3-Port PCI Express Switch” Data Sheet. 89HPES24N3. Feb. 14, 2006. Integrated Device Technology, Inc.
“DCM PCI-X Verification Services” Datasheet #2. DCM Technologies, 39675 Cedar Blvd., #220, Newark, CA 94560.
IDT. “12-lane 3-Port PCI Express Switch” Data Sheet. 89HPES12N3. Feb. 14, 2006. Integrated Device Technology, Inc.
IDT. “12-lane 3-Port PCI Express Switch” Product Brief. 89PES12N3. Feb. 15, 2006. Integrated Device Technology, Inc.
“Intel 41210 Serial to Parallel PCI Bridge Datasheet.” Intel Corporation. Sep. 2003.
“Intel 41210 Serial to Parallel PCI Bridge Design Guide.” Intel Corporation. Nov. 2003.
QuickLogic PCI Presentation. “QuickPCI™ Family of Embedded Standard Products (ESPs).”
“QL5064—QuickPCI™” DataSheet, Rev B. Feb. 2, 2000. QuickLogic.
“IDT 89HPES12N3 PCI Express Switch.” User Manual Table of Contents & Overview. Integrated Device Technology. Feb. 8, 2006.
“IDT 89HPES24N3 PCI Express Switch.” User Manual Table of Contents & Overview. Integrated Device Technology. Feb. 8, 2006.
“DCM PCI-X Verification Services” Datasheet #1. DCM Technologies, 39675 Cedar Blvd., #220, Newark, CA 94560.
“PCI-X Synthesizable Core.” inSilicon Corporation. San Jose, CA. 1999.
“IBM 133 PCI-X Bridge” Datasheet. Apr. 6, 2001.
“IBM 133 PCI-X Bridge” Datasheet 2000. IBM Microelectronics Division.
“Tsi320™ Software Initialization Application Note.” Oct. 2001. 80A600B—AN002—01. Tundra Semiconductor Corporation.
“PCI-X Bus Test Environment.” 1999. inSilicon Corporation 411 East Plumeria Dr. San Jose, CA 95134.
“1005 IDT Precise PCI-Express Family Presentation.” Integrated Device Technology.
“COMPAQ Rapid Enabler for PCI-X (CREX) Initiator Interface.” (Preliminary). Revision 0.28 Sep. 2, 1999.
“COMPAQ Rapid Enabler for PCI-X (CREX) Target Bus Interface.” (Preliminary). Revision 0.36 Sep. 2, 1999.
“Intel 41210 Serial to Parallel PCI Bridge Product Brief.” Intel Corporation. 2003.
PERICOM. “Bridge Products Road Map.” Customer Presentation. pp. 31, 33-35.
IDT. “24-lane 3-Port PCI Express Switch” Product Brief. 89PES24N3. Dec. 22, 2005. Integrated Device Technology, Inc.
“PEX 8104” Data Book. Version 0.61. Mar. 2004. PLX Technology, Inc.
“PEX 8114 PCI Express to PCI/PCI-X Bridge.” Product Brief. Version 2.0. 2004. PLX Technology, Inc.
“Tsi320™ PCI/X-to-PCI/X Bus Bridge Manual.” Jan. 2001. 80A600B—MA001—02. Tundra Semiconductor Corporation.
“Tsi320™ Dual-Mode PCI-to-PCI Bus Bridge Errata.” Sep. 2001. 80A600B—ER001—05. Tundra Semiconductor Corporation.
“Tsi320™ Dual-Mode PCI-to-PCI Bus Bridge User Manual.” Jun. 2001. 80A600B—MA001—04. Tundra Semiconductor Corporation.
“X-caliber Design Specification: PCI-2.2/PCI-X Megacell” Rev 0.99.3. Nov. 19, 1999.
Davies Ian Robert
Maine Gene
Pecone Victor Key
Davis E. Alan
Dot Hill Systems Corporation
Huffman James W.
Huynh Kim T.
Perveen Rehana
LandOfFree
Apparatus and method for adopting an orphan I/O port in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for adopting an orphan I/O port in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for adopting an orphan I/O port in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3668240