Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-10-30
2001-05-29
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S108000, C710S104000, C710S109000, C370S438000
Reexamination Certificate
active
06240478
ABSTRACT:
TECHNICAL FIELD
The present invention is directed to an apparatus and method for establishing addresses for a plurality of interconnected electronic modules.
BACKGROUND OF THE INVENTION
An electronic module, such as may be arranged at a desired location in a manufacturing process, has an internal address which is used to communicate with the module. A module, for example, may be monitored to obtain information about the module or about the environment adjacent the module. Some information might indicate, for example, the presence or absence of an article at a particular location, such as on a conveyor belt assembly.
Typically, several electronic modules are utilized. Each module has an internal address which may be set during installation of the module. In conventional systems, the internal address of each module often is set manually, such as by manipulating one or more dip-switches. As a greater number of electronic modules are used or as a module is replaced or as new modules are added, the likelihood of address-related errors increases. Accordingly, it is desirable to provide an apparatus and method in which the internal address of each module may conveniently be set during an automatic addressing process.
U.S. Pat. No. 5,204,669 to Dorfe et al. discloses a method and apparatus for dynamically assigning addresses to a plurality of fully powered programmable function modules. This patent requires that a programmable controller initiate the addressing process by transmitting an enabling signal to a first function module over a control line. The programmable controller then transmits an address to the first module.
The process continues by the first function module obtaining and storing the address from the controller. The first function module internally modifies the address and then transmits an enable signal via a control line to another module. The enable signal notifies the next module that it may receive the modified address information. The first function module then transmits the modified address to the next module over the serial communications bus.
This process continues until the last module receives its address from an adjacent preceding module. The last module has a termination circuit which sends a return signal back to the controller over a second control line after the last module receives modified address information from a preceding module. In response to the return signal, the controller may determine information about the other modules.
The addressing scheme of the Dorfe et al. Patent requires a specially configured programmable controller to initiate the addressing process. Each function module also is fully powered and configured to modify and transmit addresses to downstream modules. In addition, a second control line is required to electrically connect the last module to the programmable controller for sending the return signal back to the controller.
U.S. Pat. Nos. 5,262,771 and 5,495,575 both to Hermann et al. disclose similar methods of self-addressing individual processor units connected in a network configuration. Similar to the Dorfe et al. patent, the individual processor units in each of these patents receive address information from a preceding adjacent processor unit. The processor unit then modifies the address information for subsequent transmission to the next connected processor unit or units. These systems, however, are more complex than that disclosed in the Dorfe et al. Patent. Specifically, the systems described in the Herrmann et al. patents have additional components for accommodating multiple branches of different processor units.
SUMMARY OF THE INVENTION
One aspect of the present invention is directed to an automatic addressing system that includes a plurality of interconnected electric modules. Each of the modules includes means for activating a next adjacent module. Each module may communicate with other of the modules over a communications bus. Each of the modules is activated upon receiving an activation signal. A first of the plurality of modules to be activated sets an internal address to a default value. The other modules set their respective internal addresses upon receiving address information from the first module over the communications bus.
Another aspect of the present invention is directed to a system for automatically addressing electronic modules. The system includes a first module which has a predetermined internal address. The first module is operable to broadcast address information which is different from the address of the first module. The system also includes a second module which has an internal address which it sets upon being activated and receiving address information from the first module. The second module also is operable to broadcast a predetermined message which is received by the first module. In preferred embodiments of the present invention, the predetermined message from the second module may correspond to either (i) an acknowledgement of receiving address information or (ii) a request for address information.
Yet another aspect of the present invention is directed to a method for addressing a plurality of serially connected electronic modules. Each of the modules is operable to communicate over a communications bus. A first of the plurality of modules is initialized as a master module having a predetermined internal address. The first module provides an activation signal to an adjacent one of the plurality of modules to activate the adjacent module. The first module broadcasts address information over the communications bus, which is received at the adjacent module. The adjacent module sets an internal address upon receiving the address information from the first module. Next, the adjacent module provides an activation signal, which is effective to activate a next adjacent module in the sequence of modules.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other features of the invention will become more apparent to one skilled in the art upon consideration of the following description of the invention and the accompanying drawings in which:
FIG. 1
is a schematic representation of a system in accordance with a first embodiment of the present invention;
FIGS.
2
A and
FIG. 2B
collectively are a flow diagram illustrating a preferred addressing process in accordance with the system illustrated in
FIG. 1
;
FIG. 3
is a schematic representation of a system in accordance with a second embodiment of the present invention; and
FIG. 4
is a flow diagram illustrating a preferred addressing process in accordance with the system illustrated in FIG.
3
.
REFERENCES:
patent: 5204669 (1993-04-01), Dorfe et al.
patent: 5262771 (1993-11-01), Herrmann et al.
patent: 5452424 (1995-09-01), Goeppel
patent: 5495575 (1996-02-01), Hermann et al.
patent: 5530896 (1996-06-01), Gilbert
patent: 5586269 (1996-12-01), Kubo
patent: 5590374 (1996-12-01), Shariff et al.
patent: 5914957 (1999-06-01), Dean et al.
Eaton Corporation
Lee Thomas
Peyton Tammara
Union Marvin L.
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