Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-12-14
2001-02-13
Ray, Gopal C. (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C711S220000, C370S402000
Reexamination Certificate
active
06189062
ABSTRACT:
I. BACKGROUND OF THE INVENTION
A. Field of the Invention
The present invention relates generally to address translation, and in particular to apparatus and methods for address translation for communications handled by a bus bridge.
B. Description of the Prior Art
Computer architecture is constantly changing with technological advances and developments of new techniques. As certain elements of computer architecture change, other elements must be adjusted in some manner to compensate for these changes. Sometimes adjustments are made in hardware, sometimes in software, and sometimes in both.
One consistent change in computer architecture has been longer bit-lengths to perform various aspects of processing. Most recently, some architectures have utilized 64-bit lengths for addressing and information transfer. With the advent of 64-bit architectures comes the problem of compatibility between existing 32-bit elements and new 64-bit elements. For example, it is often necessary to transfer information between a 32-bit bus and a 64-bit bus.
When compatibility must be maintained between elements of an architecture, an intermediary device, like a bridge between buses, can adjust incompatibilities between devices. In addition to handling incompatibility issues between devices on each bus, or between the buses, a bridge transfers information. A bridge is frequently used to transfer information between buses and monitors each bus for information intended for the other bus. Upon detecting information on one bus intended for the other bus, the bridge captures the information and takes steps necessary to transfer the information to the destination device or bus. For example, if the elements have different data transfer rates, an intermediary device could perform buffering between the elements in one or both directions to alleviate the rate incompatibility.
For example, a bridge often connects the Peripheral Component Interface (PCI) Local Bus, offering multiplexed address and data lines, and which is a bus architecture designed to form a high-performance, industry standard computer. Details of the PCI Local Bus can be found in The PCI Local Bus 2.1 Specification, which is hereby incorporated by reference as background information.
The PCI has achieved a great deal of popularity with server machines having greater than four gigabytes (GB) of RAM. For such machines, PCI devices should be locatable (i.e., have addresses) above the first 32 bits (4 GB) of address space to avoid conflicts with RAM addresses. The PCI Local Bus 2.1 specification allows this through the use of 64-bit Dual Address Cycles, although the bus does not require support of those cycles. Consequently, pre-2.1 devices and most existing “2.1 compliant” devices cannot support addressing above 4 GB.
Current PCI Bridge devices provide 64-bit to 32-bit address translation in the “downstream” (primary to secondary bus) direction only. This allows 32-bit-only PCI slave devices on the secondary bus to be located arbitrarily within the full 64-bit address space of the primary bus. The 32-bit-only PCI master devices on the secondary bus, however, are confined to addressing only the first 32 bits (4 GB) of the primary bus.
There is a need for apparatus and methods for transferring information between computer elements that address issues of data transfer address width incompatibility.
II. SUMMARY OF THE INVENTION
The present invention relates to apparatus and methods for handling incompatibility issues between elements of a computer architecture. In particular, the invention relates to handling information transfer address width incompatibilities between elements of a system.
The apparatus and methods in accordance with the present invention translate an address used in communication from devices having a first addressing capability to devices having a second addressing capability greater than or equal to the first addressing capability. The invention comprises means for prestoring address translation information accessible by device identification information, means for accessing prestored address translation information using device identification information identifying one of said devices having a first addressing capability, means for receiving first address information from said one device, and means for creating a final address by combining said first address information with said prestored address translation information.
To achieve the objects and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention comprises apparatus and methods for creating an address associated with a communication between a first entity and a second entity. The apparatus and methods defined herein perform such address creation by receiving a first address information from said first entity, accessing prestored address information associated with said first entity, forming a final address by combining said first address information with said prestored address information, and communicating information to said second entity using said final address.
The disclosed invention provides a flexible structure for creating addresses used in transferring information. By utilizing page registers, the upper bits of an address can be developed prior to a transfer occurring. Then, when a device obtains the bus and begins transferring information to an entity on another bus, the upper bits are accessed and used in the transfer of information to the other bus.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description, serve to explain the principles of the invention.
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IBM Technical Disclosure Bulletin; Bus Size Independent Architecture; vol. 28, No. 8, Jan., 1986; pp. 3579-3581.
Jander Mark J.
Solomon Richard L.
LSI Logic Corporation
Ray Gopal C.
LandOfFree
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