Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
Reexamination Certificate
2002-03-28
2004-05-11
Ellis, Kevin L. (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Combining two or more values to create address
Reexamination Certificate
active
06735682
ABSTRACT:
BACKGROUND
1. Field
Embodiments of the invention relate to the field of microprocessors, and more specifically, to a circuit and method for address calculation.
2. Background
In computer systems, there are several different varieties of addressing reflecting different levels of abstraction, such as linear and physical addresses. The linear address may be calculated based on four components: Segment base, Base, Scaled Index and Offset.
Microprocessors typically include an address generating unit (AGU) to perform address calculations.
FIG. 4
depicts simplified representation of a conventional single-cycle AGU for generating linear addresses. The circuitry shown in
FIG. 4
carries out the following calculation to determine a linear address:
Address=[Base+(Index*Scale)+Offset]+Segment Base (1)
As shown above, to compute the linear address, the conventional AGU
400
first receives Base
402
, Index
404
multiplied by a Scaling factor (Scale)
420
and Offset
406
inputs via communications lines into the first 3:2 adder
412
. The multiplication of the Index
404
by the scaling factor
420
is carried out by a shifter
410
. The shifter
410
can be used for the multiplication because the Scaling factors
420
are constrained to be equal to 2
N
, where N is a positive integer or zero. The output signals
422
,
424
generated by the first 3:2 adder
412
are inputted into the second 3:2 adder
414
along with the Segment Base
408
input. Then a 2:1 adder
416
receives the output signals
426
,
428
generated by the second 3:2 adder
414
and outputs the linear address
418
in accordance with the equation (1). Accordingly, the conventional single-cycle AGU is configured to add the Base, Scaled Index and Offset together first before adding the Segment base.
To achieve higher performance, clock frequencies operating in processors continue to increase. In the past, AGUs were accustomed to performing address calculation in one clock cycle. Advances in microprocessor technology have led to shorter and shorter clock cycles. AGUs operating at higher clock frequencies may require multiple clock cycles to perform address calculation.
REFERENCES:
patent: 6209076 (2001-03-01), Blomgren
U.S. patent application Ser. No. 09/454,076, Single Cicyle, filed Dec. 2, 1999.
Chen Feng
Sager David J.
Segelken Ross A.
Ellis Kevin L.
Intel Corporation
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