Apparatus and method for accessing a branch target buffer

Details Apparatus and method for accessing a branch target buffer Apparatus and method for accessing a branch target buffer

1996-10-23

1999-02-02

Lall, Parshotam S.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711129, G06F 938

Patent

active

058676988

ABSTRACT:
A branch target buffer comprises a partitioned cache memory having for each partition a CAM array holding the least significant bits of a fetch address, a RAM holding the least significant bits of a target address, and comparators for comparing the most significant bits of the fetch and target addresses to control entry of a branch instruction into the buffer.

REFERENCES:
patent: 4084230 (1978-04-01), Matick
patent: 5136697 (1992-08-01), Johnson
patent: 5461722 (1995-10-01), Goto
patent: 5515518 (1996-05-01), Stiles et al.
patent: 5606682 (1997-02-01), McGarity
patent: 5608886 (1997-03-01), Blomgren et al.
Smith, "Cache Memories", Computing Surveys, vol. 14, No. 3, September 1982, pp. 473,477,498

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