Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-12-29
2002-09-03
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S163000
Reexamination Certificate
active
06445234
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay locked loop (DLL); and more particularly, to an apparatus and method for accelerating an initial lock time of the DLL in a high rate double data rate (DDR) synchronous random access memory (SDRAM).
2. Prior Art of the Invention
In general, a DLL corrects skew between an external synchronization clock signal and an internal clock signal, which is necessarily needed for the high rate memory device, e.g., a DDR SDRAM.
In conventional DLLS, a skewed internal clock signal is repeatedly compared with a reference external clock signal and applied by a unit delay time. The comparison is repeated until skew between the reference external clock signal and the skewed internal clock signal is smaller than the unit delay time, that is, an initial operation of the DLL is completed.
However, in the conventional DLL, the internal clock signal is repeatedly delayed by the unit delay time, and correction result, that is, a delayed internal clock signal, is compared with the reference external clock signal at every delay. Accordingly, the number of comparison is large and the large number of comparison makes an initial lock time of the DLL too long. For example, assume that 0.2 nsec unit delay time is used, in order to perform 8 nsec delay operation by using the conventional method which compares the phase of the DLL clock signal with the reference clock signal at every eight clocks, the correction is completed after at least 40 comparisons, that is, 320 clocks. This problem is critical to the high rate device.
SUMMARY OF THE INVENTION
Therefore, an object of the invention is to provide an apparatus and method for accelerating an initial lock time of the DLL which repeatedly applies multiple unit delay time along with unit delay time to a reference clock signal or an internal clock signal.
In accordance with one embodiment of the present invention, there is provided an apparatus for accelerating an initial lock time of DLL (Delayed Locked Loop) which removes skew between an external synchronization clock signal and an internal clock signal, comprising: means for generating a reference clock signal based on the external synchronization clock signal; means for applying a unit delay time and a multiple unit delay time to the internal clock signal and for comparing phases of the internal clock signal, a unit delayed internal clock signal and a multiple unit delayed internal clock signal with a phase of the reference clock signal; means for selecting an amount of delay time based on a comparison result; means for delaying the internal clock signal by the amount of delay time based on a selected amount of delay time; and means for generating a modeled delay clock signal corresponding to a delayed internal clock signal and for providing the modeled delay clock signal with said means for applying a unit delay and a multiple unit delay time.
In accordance with one embodiment of the present invention, there is provided an apparatus for accelerating an initial lock time of DLL (Delayed Locked Loop) which removes skew between an external synchronization clock signal and an internal clock signal, comprising: means for generating a reference clock signal based on the external synchronization clock signal; means for applying a unit delay time and a multiple unit delay time to the reference clock signal and for comparing phases of the reference clock signal, a unit delayed reference clock signal and a multiple unit delayed reference clock signal with a phase of the internal clock signal; means for selecting an amount of delay time based on a comparison result; means for delaying the reference clock signal by the amount of delay time based on a selected amount of delay time; and means for generating a modeled delay clock signal corresponding to a delayed reference clock signal and for providing the modeled delay clock signal with said means for applying a unit delay and a multiple unit delay time.
In accordance with one embodiment of the present invention, there is provided a method for accelerating an initial lock time of DLL (Delayed Locked Loop) which removes skew between an external synchronization clock signal and an internal clock signal, comprising the steps of: a) receiving a reference clock signal an internal clock signal; b) comparing the reference clock signal with the internal clock signal and determining an amount of delay time between the two clock signals; c) reducing the amount of delay time by one unit delay if the amount of the delay time is larger than a predetermined value; d) increasing the amount of delay time by one unit delay or a number of unit delay time if the amount of the delay time is smaller than the predetermined value; and e) repeating said steps a) to d) until a phase difference between the reference clock signal and the internal clock signal is smaller than the unit delay.
REFERENCES:
patent: 5355037 (1994-10-01), Andressen et al.
patent: 5771264 (1998-06-01), Lane
patent: 6067272 (2000-05-01), Foss et al.
patent: 6125157 (2000-09-01), Donnelly et al.
Han Jong-Hee
Yoon Min-Ho
Callahan Timothy P.
Hyundai Electronics Industries Co,. Ltd.
Jacobson & Holman PLLC
Nguyen Linh
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