Semiconductor memory device allowing simultaneous inputting...

Details Semiconductor memory device allowing simultaneous inputting... Semiconductor memory device allowing simultaneous inputting...

2001-10-19

2002-09-17

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189011, C365S189070

Reexamination Certificate

active

06452861

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memo device, and more specifically, to a semiconductor memory device allowing data signals externally supplied to be written into N memory cells that a selected.
2. Description of the Background Art
Conventionally, a test for detecting a defective memory cell is conducted for a semiconductor memory such as a synchronous dynamic random access memory (hereinafter referred to as SDRAM) before shipping.
FIG. 17
is a block diagram representing the relations among a column address signal Y, data signals DQ
0
to DQ
3
, and a bit line pair BL, /BL in a x16 configuration of such an SDRAM. In
FIG. 17
, a memory cell MC is arranged in each intersection portion of bit line pair BL, /BL and a word line WL, and a sense amplifier
50
is provided to each bit line pair BL, /BL. A plurality of bit line pairs BL, /BL are divided into groups of four bit line pairs in advance. Two groups are shown in FIG.
17
. For the two groups, unique column address signals Y=n−1, Y=n are respectively assigned. The first to fourth bit line pairs BL, /BL of each group are respectively used for inputting/outputting of data signals DQ
0
to DQ
3
.
In such an arrangement, a faulty read of a data signal from a memory cell MC is most likely to occur when a data signal of a memory cell MC of interest which is the target of testing (cell MC of interest is shown by a solid-filled black circle in
FIG. 17
) is read in a situation where a data signal of the logic low or “L” level is written in the cell MC of interest, data signals of the “L” level are written in memory cells MC on either side of that memory cell MC of interest in the same row, and data signals of the logic high or “H” level are written in other memory cells MC in the same row.
Since the “L” level is written in cell MC of interest, when word line WL attains the select level while sense amplifier
50
is rendered active, bit line BL of a column of cell MC of interest attains the “L” level, while bit line /BL attains the “H” level. Since the “L” level is written in memory cells MC on either side of cell MC of interest, bit lines BL of the corresponding columns attain the “L” level, while bit lines /BL attain the “H” level. Consequently, bit line BL of the column of cell MC of interest and bit line /BL of the column on one side thereof would attain opposite levels, while bit line /BL of the column of cell MC of interest and bit line BL of the column on the other side thereof would attain opposite levels, so that the coupling noise becomes great.
In addition, since the “H” level is written in other memory cells MC, when word line WL attains the select level and sense amplifier
50
is rendered active, a ground noise is generated due to the reading of the data signal of the “H” level. Thus, faulty read of the data signal having the “L” level from cell MC of interest is likely to occur.
Thus, the sense operation margin becomes the smallest when the test pattern is employed in which the “L” level is written into three memory cells MC of the same row while the “H” level is written to other memory cells MC.
When an attempt is made to write the test pattern as the one shown in
FIG. 17
with a tester, there is a need to make data signal DQ
3
an inverted data signal of data signals DQ
0
to DQ
2
for the group in which column address signal Y is n−1, while there is a need to make data signals DQ
0
, DQ
1
the inverted data signals of data signals DQ
2
, DQ
3
for the group in which column address signal Y is n. In other words, the combination of data signals DQ to be inverted must be changed according to column address signal Y. and an extremely complicated pattern program would be required to effect such change so that the implementation becomes difficult.
SUMMARY OF THE INVENTION
Thus, the principal object of the present invention is to provide a semiconductor memory device that allows easy writing of a test pattern.
The semiconductor memory device according to the present invention is provided with a write data inverting circuit for receiving externally supplied N data signals and for outputting each data signal inverted or uninverted based on a data control signal, a write circuit for writing N data signals output from the write data inverting circuit into N memory cells that are rendered active by a row select circuit via N bit line pairs selected by a column select circuit, and a plurality of address signal input terminals for inputting a row address signal and a column address signal at different timing, where the data control signal is input along with the column address signal using an address signal input terminal among the plurality of address signal input terminals which is not used for inputting of the column address signal. Thus, each data signal, inverted or uninverted, can be written into a memory cell by inputting N data signals of the same logic and by inputting a column address signal and a data control signal via a plurality of address signal input terminals. In this manner, a test pattern can be easily written without using a complicated pattern program. Moreover, the data control signal is input along with the column address signal using an address signal input terminal not used for inputting of the column address signal so that no increase in the number of signal input terminals and in the write time takes place.
Preferably, the semiconductor memory device according to the present invention is further provided with a read circuit for reading data signals of N memory cells rendered active by the row select circuit via N bit line pairs selected by the column select circuit, a read data inverting circuit for receiving N data signals read by the read circuit and for outputting each data signal inverted or uninverted based on the data control signal, and N data input/output terminals for outputting to outside N data signals output from the read data inverting circuit and for supplying N data signals to the write data inverting circuit (
32
,
34
) from outside. In this case, a memory cell that is the test target can be determined to be normal when the logic of an input data signal matches the logic of an output data signal.
More preferably, the number N of bit line pairs selected by the column select circuit can be changed, and each of the write data inverting circuit and the read data inverting circuit outputs each data signal inverted or uninverted based on the data control signal and a word configuration instruction signal indicating the number N of bit line pairs selected by the column select circuit. In this case, a data signal can be inverted according to the word configuration.
More preferably, the semiconductor memory device according to the present invention is further provided with a decoder for causing each of N inversion instruction signals corresponding to N data signals to attain the active level or inactive level based on the word configuration instruction signal and the data control signal, where the write data inverting circuit includes N first inverting circuits which are respectively provided corresponding to externally supplied N data signals and each of which inverts a corresponding data signal when a corresponding inversion instruction signal is at the active level and allows the corresponding data signal to pass through without inversion when the corresponding inversion instruction signal is at the inactive level, and the read data inverting circuit includes N second inverting circuits which are respectively provided corresponding to N data signals read by the read circuit and each of which inverts a corresponding data signal when a corresponding inversion instruction signal is at the active level and allows the corresponding data signal to pass through without inversion when the corresponding inversion instruction signal is at the inactive level. In this case, the write data inverting circuit and the read data inverting circuit can be configured with ease.
More preferably, the semiconductor me

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